Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Analogue PLL",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Clocking ICs reduce component numbers from
Cirrus Logic, which we summarised at the time by saying "The CS2000 offers both a clock generator feature and clock cleanup in a single IC, reducing the number of components and board space required in audio systems".
Several months prior to that,
we featured the news release Synchroniser solves timing challenges from
Zarlink Semiconductor: "A single-chip ultra-low-jitter synchroniser solves the timing challenges posed by the popular AdvancedTCA, AMC and MicroTCA architectures".
In December 2005, we covered the news from Zarlink Semiconductor
concerning its ZL30116 and ZL30119
- take a look at Synchronisers keep multiservice clocks together
which says: "The feature-rich ZL30116 and ZL30119 phase locked loops are the lowest jitter and smallest devices for managing Sonet/SDH Stratum 3 synchronisation at OC-48/STM-16 rates".
Take a look also at the news release from Zarlink Semiconductor, Digital PLL shrinks for optical line cards,
as well as Digital and analogue PLLs combine for Sonet from Zarlink Semiconductor,
and Digital PLLs claim carrier-class performance from Zarlink Semiconductor.
See also:
TDM switching family integrates Stratum 3 timing
(February 2004)
A new family of nine low- to mid-density TDM/TSI switches features the industry's widest range of programmable and integrated features
Standards-compliant timing module crams more in
(December 2003)
The ZL30461 is billed as the industry's smallest, most fully featured timing product for central timing cards in Sonet/SDH systems that provide clocking frequencies up to 155.52MHz
Analogue PLL claims best fit for line cards
(November 2003)
A new analogue timing chip is claimed to deliver the industry's best combination of performance and features for Sonet/SDH line cards operating at up to OC-12/STM-4 rates
PLL's six clocks simplfy line card design
(August 2003)
Zarlink Semiconductor has a new high-performance analogue PLL timing chip for optical line cards operating at up to OC-192 rates
Analogue PLL features six clocks
(May 2003)
Zarlink Semiconductor has launched an analogue timing chip with six low-jitter output clocks - more than any other competing product - for optical line cards
Arrays aim for mid-volume ASIC market
(May 2003)
AccelArray technology aims to meet customer requirements for low cost and minimal design cycles using Fujitsu's proven design and process technology leadership
Timing module has it all for high-speed line cards
(April 2003)
Zarlink Semiconductor has launched the industry's most compact, fully featured timing module for high-speed line cards in network access equipment
Front ends boost hi-res monitor performance
(April 2003)
Two new high-speed analogue front ends offer new levels of high resolution video performance for UXGA monitor applications