Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "ATPG (automatic test program generation)",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Scan compression eases HDTV IC test regime from
Synopsys, which we summarised at the time by saying "DFT MAX automatically implements scan compression on-chip, which can reduce the amount of data required to test each manufactured part by 95% or more".
Earlier in the week,
we featured the news release Boundary scan is optimised for flying probes from
Goepel Electronic: "Tools enable an unrivalled level of interaction between flying probe access and boundary scan access for board level test applications, embracing all phases of IEEE1149.1 applications".
In October 2007, we covered the news from Synopsys
concerning its Galaxy
- take a look at IC test generator takes power criteria onboard
which says: "The TetraMax automatic test pattern generation now creates tests reflecting designers' power budgets".
Take a look also at the news release from Synopsys, Technology improves testing accuracy,
as well as Alliance focuses on automotive component testing from Advantest (Europe),
and Advanced LSI ICs are designed for testing from Cadence Design Systems.
See also:
Reference methodology aids ARM-based design
(October 2006)
Cadence Design Systems is collaborating with ARM to expand the breadth of their joint reference methodology with the addition of Encounter Test timing and power-aware technology
Test software improves 90nm delay defect coverage
(October 2006)
Azul Systems has directed its manufacturing test generation development process to Cadence Encounter True-Time Test ATPG solution
Links accelerate IC yield ramp
(October 2006)
Links between TetraMAX automatic test pattern generation diagnostics and the Odyssey yield management system accelerate yield ramp at foundries
Software adds more insight into yield data
(October 2006)
Yield Insight is a systematic yield learning solution that leverages detailed manufacturing test data to provide detailed sub-die-level failure and performance monitoring capabilities
Design-for-test tool runs at-speed
(October 2006)
LogicVision has unveiled its ScanBurst tool and has partnered with Mentor Graphics to deliver a unique and improved at-speed test solution for high-speed nanometre designs
Improved analysis of manufacturing failures
(October 2006)
The Mentor Graphics YieldAssist tool now supports an automated, server-based use model for high volume diagnosis of wafer test failures
Compression software improves ATPG
(October 2006)
TestKompress 2007 is an enhanced version of the ground-breaking tool from Mentor Graphics that introduced scan test pattern compression to the marketplace
News on the New ATPG technology from Synopsys
(October 2006)
Automatic test pattern generation technology is designed to increase the quality of manufacturing tests by targeting small delay defects
Automatic test pattern generator accelerated
(September 2006)
Enhancements to the TetraMAX automatic test pattern generator result in a typical speedup of three times or more in runtime performance across all design styles
Design and system interconnect go with the flow
(July 2006)
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0
Award for Design-for-Test Team
(July 2006)
Mentor Graphics Design-for-Test Team Awarded IEEE CEDA Donald Pederson Best Paper Award
Timing-aware test generation cuts design delays
(June 2006)
Comit Systems has standardised its automatic test pattern generation (ATPG) flow on Cadence Encounter Test
Power-management methodology is enhanced
(February 2006)
The Silicon Design Chain Initiative has published announced a second, enhanced version of its power-management methodology
Kawasaki Micro maximizes delay test coverage
(November 2005)
Kawasaki Microelectronics has selected Cadence Encounter True-Time technology, the delay test ATPG that uses design timing to automatically generate faster-than-at-speed delay tests
Adaptive scan technology reduces tester costs
(November 2005)
Genesis Microchip, supplier of display image ICs, has successfully deployed DFT MAX adaptive scan technology to reduce tester costs
Structured ASICs aid modem design
(September 2005)
HardCopy structured ASICs from Altera have been used in the IPX-5100, a modem designed by Efficient Channel Coding (ECC) for broadband Internet access through satellites
TSMC integrates nanometre design platforms
(June 2005)
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's latest reference flow
Scan test tool joins reference flow
(June 2005)
Taiwan Semiconductor Manufacturing Company (TSMC) has added the TestKompress scan test tool to its Reference Flow 6.0
Structured ASICs speed satellite modems to market
(January 2005)
Mark Vanderaar and Ganesh Narayanaswamy describe how HardCopy structured ASICs from Altera were used in a modem designed by Efficient Channel Coding for broadband Internet access through satellites
ATPG starter packages improve ASIC quality
(October 2004)
The DFT-PRO 100 and 200 Series of automatic test program generator starter packages include the essential design-for-test tools for comprehensive ASIC testing
Novel tool promises to boost nanometre yields
(October 2004)
Cadence Encounter Diagnostics is billed as the semiconductor industry's first yield diagnostics tool
Software automates test generation
(October 2004)
Mentor Graphics has added new automated functionality to its FastScan automatic test pattern generation tool and its TestKompress embedded deterministic test tool
Timing delay tester tackles nanometre designs
(May 2004)
Cadence Design Systems reckons it has brought timing to the manufacturing floor with True-Time delay test for processes at 130nm and below
News on the DFT Compiler and TetraMAX ATPG from Synopsys
(April 2004)
The new releases of DFT Compiler and TetraMAX ATPG have improved design-for-test and automatic test pattern generation performance and pattern count for deep submicron designs
Deterministic logic BIST cuts SoC test costs
(September 2003)
Toshiba has taped out a high-performance digital image processor chip targeting consumer multimedia applications using Synopsys DFT Compiler SoCBIST's deterministic logic BIST capability
Test solution aids core-based design development
(March 2003)
Synopsys has added a comprehensive test automation solution for core-based designs to its DFT Compiler, a key component of the Galaxy design platform
Bigger faster ASICs are a speciality
(November 2002)
The Texas Instruments ASIC team is targeting the largest and most complex products by leveraging its advanced semiconductor process technology, embedded IP, and advanced packaging and design tools
Logic BIST reduces SoC test data and time
(October 2002)
Synopsys has entered the logic BIST market with DFT Compiler SoCBIST, offering deterministic logic BIST capabilities
Addon speeds automatic test pattern generation
(September 2002)
TetraMAX TenX provides distributed processing for automatic test pattern generation
Faraday builds in testability with Mentor
(July 2002)
Faraday Technology Corp has selected Mentor Graphics design-for-test (DFT) tools for its SoC design flows
DFT helps Bay Montego get it right first time
(July 2002)
Bay Microsystems has recently made the first customer shipment of its 'right first time' 10Gbit/s Montego internetworking processor, developed using SynTest's DFT tools and services
Failure diagnostics under development
(May 2002)
Advantest is to develop a fast, accurate failure diagnostics solution for deep-submicron high-speed SoC designs leveraging TetraMax automatic test pattern generation technology from Synopsys
Advantest checks tool compatibility before launch
(May 2002)
Advantest is working with Mentor Graphics to ensure full compatibility between its new SoC failure diagnostics tool and Mentor's suite of FastScan automatic test pattern generation tools
Design-for-test tool successfully run on ARM core
(April 2002)
The LBISTArchitect tool from Mentor Graphics has been successfully used to implement logic built-in self test (BIST) for the ARM966E-S microprocessor core