Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "BIST (built-in self-test)",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Technology meets 65nm challenges from
Faraday Technology, which we summarised at the time by saying "Faraday Technology's UMC 65nm LL allows users to generate memory options including words, bits and aspect ratios, while retaining the desired area, performance and power
specification".
Several months prior to that,
we featured the news release Standards working group calls for feedback from
IEEE P1581 Working Group: "The IEEE P1581 has set up its working group to define a low-overhead design-for-test methodology to be implemented in memory devices".
In February 2007, we covered the news from LogicVision Europe
- take a look at Wintegra signs up for memory BIST
which says: "Wintegra has selected LogicVision's leading-edge memory BIST solution, ETMemory, to help it meet its silicon manufacturing quality goals".
Take a look also at the news release from LogicVision Europe, Embedded memory tests aid parallel processing,
as well as Cell-based ASICs drop in for FPGA replacement from AMI Semiconductor,
and Serdes chipset speeds past 1Gbit/s from National Semiconductor.
See also:
News on the EmBISTRx from ARM
(October 2006)
Embedded memory test and repair system is tightly integrated with the ARM Advantage and Metro memory compilers
Software adds more insight into yield data
(October 2006)
Yield Insight is a systematic yield learning solution that leverages detailed manufacturing test data to provide detailed sub-die-level failure and performance monitoring capabilities
Design-for-test tool runs at-speed
(October 2006)
LogicVision has unveiled its ScanBurst tool and has partnered with Mentor Graphics to deliver a unique and improved at-speed test solution for high-speed nanometre designs
GDA Technologies adopts test IP for serdes
(July 2006)
LogicVision and GDA Technologies are to deliver design services for high speed I/O test with LogicVision's comprehensive at-speed test IP for high speed serdes circuits
Board Test Workshop comes to the UK
(April 2006)
The Board Test Workshop Organising Committee has scheduled another EBTW event in association with the 2006 European Test Symposium
Standard cell ASICs set to exploit market void
(April 2006)
A flexible 130nm standard cell technology offers a low-cost high-performance ASIC solution for broad-based applications
Prototyping is cost-effective for smaller ASICs
(March 2006)
Two new series of third-generation motherboards bring the performance of the Hardi ASIC Prototyping System (HAPS) for multi-million-gate ASICs to smaller designs
Serdes converges on 10Gbit/s applications
(February 2006)
The XFI serdes core offers single-lane operation up to 11.1Gbit/s to allow for forward error correction
Development kit targets DSP-rich FPGA design
(May 2005)
The Virtex-4 XtremeDSP Development Kit will enable designers to immediately leverage Xilinx' new DSP-rich Virtex-4 SX FPGAs in new advanced FPGA designs
Software offers superior internal test structures
(March 2005)
Cadence Encounter Test Architect is billed as the industry's first full-chip test architecture development product
Serdes chipset survives automotive environments
(February 2005)
The SCAN921025H serialiser and SCAN921226H deserialiser deliver up to 10bit digital data at 20 to 80MHz over a single point-to-point differential interconnect in backplanes or cable
LVDS extends reach and drive
(November 2004)
National Semiconductor has added three new high-speed analogue interface chips to its industry leading portfolio of LVDS (low voltage differential signalling) products
BIST tool tackles embedded memories
(October 2004)
New enhancements to the MBISTArchitect built-in self-test (BIST) tool provide thorough on-chip testing for embedded memories generated by Artisan Components
Interface speeds QDR memory access
(July 2004)
LSI Logic Corp has developed the industry's highest speed physical layer interface to QDR-2 SRAM memory, enabling the next generation of high-end network routers, switches and host bus adapters
Reference flow takes design platform onboard
(June 2004)
The latest TSMC reference flow incorporates unique features and innovations of Synopsys' Galaxy design platform for designs at 130nm, 90nm and below
Deterministic logic BIST cuts SoC test costs
(September 2003)
Toshiba has taped out a high-performance digital image processor chip targeting consumer multimedia applications using Synopsys DFT Compiler SoCBIST's deterministic logic BIST capability
Arrays aim for mid-volume ASIC market
(May 2003)
AccelArray technology aims to meet customer requirements for low cost and minimal design cycles using Fujitsu's proven design and process technology leadership
Less power needed for quad transceiver
(February 2003)
Fairchild Semiconductor has a new quad-channel transceiver that uses 25% less power than comparable devices across an operating range from 100Mbit/s to 1.36Gbit/s
LVDS technology improves system-level designs
(January 2003)
Three new LVDS-based products aim to provide complete, system-level solutions for a wide variety of applications ranging from high-speed interface and integrated circuit testing to medical imaging
Bigger faster ASICs are a speciality
(November 2002)
The Texas Instruments ASIC team is targeting the largest and most complex products by leveraging its advanced semiconductor process technology, embedded IP, and advanced packaging and design tools
Logic BIST reduces SoC test data and time
(October 2002)
Synopsys has entered the logic BIST market with DFT Compiler SoCBIST, offering deterministic logic BIST capabilities
BIST tool boosts SoC memory reliability
(September 2002)
Mentor Graphics has increased its support for Artisan Components embedded memory products
Serdes quadruples comms capacity
(September 2002)
National Semiconductor has entered the multigigabit serdes market with the introduction of a best-in-class 2.5Gbit/s transceiver optimised for backplane, cable and fibre optical applications
IP library gains memory resources
(July 2002)
A new full line of memory intellectual property (IP) includes memory models, memory controllers and memory BIST
Faraday builds in testability with Mentor
(July 2002)
Faraday Technology Corp has selected Mentor Graphics design-for-test (DFT) tools for its SoC design flows
DFT helps Bay Montego get it right first time
(July 2002)
Bay Microsystems has recently made the first customer shipment of its 'right first time' 10Gbit/s Montego internetworking processor, developed using SynTest's DFT tools and services
Debugger gets to the root of embedded memories
(July 2002)
TurboDebug-SoC/Memory from SynTest Technologies reduces the cost of test and debug for SoCs with large BISTed embedded memories
Verification of interoperability
(May 2002)
LogicVision has successfully completed interoperability testing with Verplex's Conformal logic equivalence checker (LEC) formal verification product
Ricoh adopts Mentor Graphics LBISTArchitect
(April 2002)
Ricoh has adopted the LBISTArchitect logic built-in-self-test (BIST) solution from Mentor Graphics
Trade-in deal to woo Avant! users
(April 2002)
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software
News on the LBISTArchitect from Mentor Graphics UK
(April 2002)
The LBISTArchitect tool from Mentor Graphics has been successfully used to implement logic built-in self test (BIST) for the ARM966E-S microprocessor core
LVDS gets faster and faster
(February 2002)
National Semiconductor has the industry's fastest 10bit LVDS serialiser/deserialiser chipset for high-speed data transfer over a single differential pair
MoSys turns to Mentor to reduce memory test costs
(January 2002)
MoSys and Mentor Graphics are working to qualify and deliver memory built-in self-test (BIST) solutions optimised for the MoSys 1T-SRAM family of high-density embedded memories to reduce test cost
Analysis tool checks testability of RTL code
(January 2002)
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level