Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "DRC",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Chip design software stacks up 3D advantages from
Micro Magic, which we summarised at the time by saying "A novel design technique known as 'through-Si via wafer stacking' offers a new dimension for chip designs".
A few weeks before,
we featured the news release Beta testers wanted for IC design rule checker from
Polyteda Software Corporation: "Polyteda Software is offering free access to the beta version of a new tool that allows users to perform a full set of logical operations and density checks on IC layers".
In May 2007, we covered the news from Mentor Graphics UK
concerning its Calibre LFD
- take a look at Infineon and Chartered use litho-friendly design
which says: "Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology".
Take a look also at the news release from Softjin Technologies, EDA tool stands test of comparison,
as well as Power management technology updated from Zarlink Semiconductor,
and Viewer offers a quick look at IC designs from Micro Magic.
See also:
Compiler technology complements HyperTransport
(January 2007)
CebaTech has joined the HyperTransport Technology Consortium
PVS rule files now for 180nm technology
(December 2006)
Synopsys' Hercules Physical Verification Suite (PVS) rule files are now available for Tower Semiconductor's release of 180nm high-voltage technology
Advanced quad development platform unveiled
(December 2006)
Lyrtech has launched the Virtex-4 version of its best-selling SignalMaster Quad advanced development platform
Software gives early view of manufacturing defects
(November 2006)
InShape is billed as the first model-based full-chip design manufacturability checker that predicts accurate silicon shapes
Process technologies improve power management
(November 2006)
Zarlink Semiconductor has announced the release of an enhanced WPX and WPY process with a high beta early voltage lateral PNP transistor
BiCMOS process has powerful intelligence
(November 2006)
Submicron BiCMOS process technology specifically addresses increasing customer demand for control and intelligence in power management chips
HyperTransport developers to meet in Santa Clara
(October 2006)
The annual HyperTransport Technology Developers Conference will take place on Thursday 26th October 2006, at the Santa Clara Marriott Hotel in Santa Clara, California
News on the Calibre nmDRC from Mentor Graphics UK
(July 2006)
Mentor Graphics Corporation has announced that Calibre nmDRC, Mentor's next generation physical verification tool, is fully supported and qualified on the new Intel Dual-Core Xeon 5160 Processor
Mentor Graphics Calibre nmDRC adopted by UMC
(July 2006)
Mentor Graphics Calibre nmDRC adopted by UMC to address shifting requirements for sign-off
Easy to use tanner tools pro 12.1
(July 2006)
Tanner EDA has announced its analog and mixed-signal design tool suite, Tanner Tools 12.1, which has been upgraded and tightly integrated for rapid design flow
Extended RTL-to-GDSII low-power reference design
(July 2006)
Extended RTL-to-GDSII low-power reference design flow for the latest 65-nanometer (nm) process offered by the IBM-Chartered Semiconductor Manufacturing-Samsung Common Platform technology initiative
Design and system interconnect go with the flow
(July 2006)
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0
News on the Calibre nmDRC from Mentor Graphics UK
(July 2006)
Calibre nmDRC redefines traditional design rule checking by dramatically reducing total cycle time and integrating critical elements such as critical area analysis and critical feature identification
Layout optimisation engine removes IC hotspots
(July 2006)
A novel tool automatically optimises design tape-out data to eliminate lithography related hot spots
DFM technologies are qualified for 65nm process
(May 2006)
An integrated set of best-in-class tools from the Calibre design-to-silicon platform supports TSMC's 65nm technology
Workstation helps explore FPGA coprocessing
(April 2006)
A computing workstation couples the AMD Opteron processor with a dynamically reconfigurable coprocessor module populated with Virtex-4 FPGA devices
Reference flow speeds mixed-signal design
(April 2006)
An analogue mixed-signal reference flow addresses the needs of designers developing ICs for the consumer, networking and wireless markets
Design tools support Common Platform
(April 2006)
Tools from the Calibre design-to-silicon platform are qualified and available to support design for the IBM/Chartered/Samsung 65nm process Common Platform technology
Direct to disk recorder logs re-entry data
(March 2006)
StreamStor is an integral part of the data acquisition system on the Arianespace Ariane 5
Upgraded RF process promises higher yields
(February 2006)
Zarlink's updated H-Series processes now deliver more die per wafer and improved yields, resulting in the industry's most cost-effective process for fabricating analogue RF microchips
Encryption secures process design kits
(December 2005)
IBM has adopted patent pending Calibre encryption technology for use with its 90, 65 and 45nm process design kits
Budget PCB design system adds a 3D view
(November 2005)
Available now from Adept Scientific is the 9th edition of the Easy-PC printed circuit board and schematic design system from Number One Systems
Tools boost mixed-signal productivity
(November 2005)
Tanner EDA has upgraded its Tanner Tools L-Edit design tool for layout, verification, and placement and routing of analogue and mixed-signal integrated circuits, ASICs and MEMS
News on the Quartz DRC from Magma Design Automation
(September 2005)
Magma Design Automation, a provider of semiconductor design software, has announced the availability of Quartz DRC, a key component of the company's recently announced Cobra 2005.03 release
Verification and extraction tools integrated
(August 2005)
Mentor Graphics' Calibre physical verification and extraction tools are now fully integrated into the Cadence design creation environment
High-voltage routing checker works in 3D
(May 2005)
Spacing Synthesizer is a novel 2D and 3D routing checker for high voltage PCBs, such as those carrying power supply circuits or boards designed for intrinsically safe applications
MEMS design package checks rules as you go
(April 2005)
L-Edit MEMS Design is the new flagship micro-electromechanical systems design package from Tanner EDA
Upgrade for mixed-signal IC design platform
(April 2005)
L-Edit v11.1 is the latest release of the flagship analogue and mixed-signal IC design platform from Tanner EDA
3D package integrates with PCB design suite
(March 2005)
EM Designer 4.4 now supports integration with Zuken's enterprise level PCB design suite, CR-5000 Board Designer
Package adds a new dimension to PCB design
(February 2005)
A new package offers a novel solution for applications that require advanced PCB design with 3D functionality
Budget design package boasts high-end features
(January 2005)
Easy-PC 8 is the latest version of the world famous windows-based software tool for printed circuit board design and schematics capture
Micrel opts for intelligent design rules
(October 2004)
Micrel has adopted the DesignRuleBuilder component of the Silicon Insight toolkit for semiconductor technology development
Node highlighting aids mixed-signal design
(June 2004)
Tanner EDA has been demonstrating a key upgrade to its L-Edit Pro analogue/mixed-signal layout tool for IC design at DAC 2004
Software automates library cell creation
(May 2004)
ZenCell Factory is a novel automated library cell creation solution for standard cell-based design