Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "EDIF",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Layout tool teaches chip design from
EDA Solutions, which we summarised at the time by saying "IC Mask Design uses Tanner's L-Edit layout tool for its training courses".
A few weeks before,
we featured the news release EDA tool suite features 11 upgrades from
EDA Solutions: "Tanner Tools 12.2 is the latest release of the Windows-based EDA tool suite for analogue, mixed-signal and MEMS design from Tanner EDA".
In November 2006, we covered the news from Aldec
concerning its System Verification Environment
- take a look at Verification environment moves up to Stratix III
which says: "Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family".
Take a look also at the news release from Synopsys, E-Tools takes interoperability award,
as well as Improved C++ Support In SystemC Synthesis Tool from Celoxica,
and Kit accelerates programmable SoC development from Celoxica.
See also:
System level design comes to Xilinx FPGAs
(March 2006)
The Celoxica ESL Starter Kit provides an out-of-the-box solution for Xilinx FPGA designers who want to pilot and deploy system level design tools and methodologies into their development flows
Environment brings mixed-signal tools together
(March 2006)
A new design environment for schematic capture is an integrated suite of affordable Tanner analogue and mixed-signal design capture, simulation, layout, design rule checking and verification tools
Compiler supports latest SystemC standard
(January 2006)
The new Agility Compiler for SystemC synthesis can generate RTL descriptions from transaction level models for popular ASIC/SoC synthesis flows and gate-level EDIF netlists for PLDs
Software agreement speeds FPGA design support
(December 2005)
A new OEM agreement gives FPGA designers access to a range of performance and productivity benefits using Precision Synthesis within the QuickLogic QuickWorks environment
Timing analysis works with PCB and FPGA flows
(November 2005)
Chronology has expanded its TimingDesigner interactive timing analysis and timing diagram product to include tighter integration with vendor-specific board design and FPGA flows
Timing analysis speeds data interface design
(November 2005)
Chronology has expanded its TimingDesigner interactive timing analysis and timing diagram product to include tighter integration with vendor-specific board design and FPGA flows
IP core adds serial FPDP datalinks
(August 2005)
Available now from Vmetro is a serial FPDP IP core for use on its range of Xilinx Virtex-II Pro FPGA products
FFT cores promise faster real-time processing
(July 2005)
RF Engines has developed a library containing more than 60 fast Fourier transform (FFT) cores for use in Xilinx FPGA devices
System-level design supports structured ASICs
(June 2005)
Celoxica is supporting Altera's HardCopy II structured ASIC family with its Agility Compiler for SystemC and the DK Design Suite
Gate-level debugger is easy to customise
(June 2005)
GateVision Pro is a high-performance gate-level debugging tool that offers an open API that allows chip designers to customise and implement their own debugging functions
Compact cores create flexible resampling filters
(June 2005)
A new range of fractional resampling architectures for FPGAs can be used to perform up-sampling or down-sampling of high-speed digital signals
Suite delivers full software to silicon flow
(May 2005)
The fourth generation of the DK Design Suite is claimed to reset the bar for C-synthesis performance and deeply embeds the technology in standard SoC design flows
Compiler enables working silicon from SystemC
(February 2005)
Agility Compiler for SystemC includes an array of advanced system design capabilities for the synthesis of SystemC models to hardware
RTL synthesis upgrades FPGA design software
(January 2005)
Lattice Semiconductor has announced the immediate availability of the Mentor Graphics' Precision RTL synthesis tool for customer use
Editor gets to grips with VHDL and Verilog
(December 2004)
Now available free of charge from HDL Works, Scriptum is a high end text editor that integrates with the company's Ease and HDL Companion tools
Software does the lot for Actel FPGAs
(December 2004)
Aldec has released a special Actel Edition of Active-HDL 6.3, offering easy-to-use pushbutton integration with Actel's Designer series advanced place-and-route software
ESL design environment covers more devices
(December 2004)
Version 3.1 of the DK Design Suite provides high-level system codesign, verification and C-based synthesis for complex algorithm implementation to high-density FPGA and programmable SoC devices
Compiler automates SystemC synthesis
(June 2004)
The Agility compiler synthesises SystemC directly to high-density FPGA and programmable SoC logic and generates RTL VHDL and Verilog for SoC design
Software speeds Stratix II designs
(March 2004)
Aldec now supports Altera's latest high-density Stratix II FPGA device family with its graphical design entry tool, Design Flow Manager, as well as its mixed-VHDL and Verilog simulator
FPGA design environment gives best of both worlds
(November 2003)
Active-HDL+C is an integrated FPGA design environment that combines Aldec's Active-HDL design entry and mixed-HDL simulation technology with Celoxica's DK engine for C-synthesis and cosimulation
Kaufman Award for Newton
(October 2003)
A Richard Newton, Dean of the College of Engineering at the University of California, Berkeley, is this year's recipient of the prestigious Phil Kaufman Award
Customised design suite speeds FPGA development
(October 2003)
A custom edition of the Celoxica DK Design Suite will be included with the recently announced Xilinx ISE Embedded Development Kit v6.1
Budget entry to IC layout and verification
(October 2003)
L-Edit Pro V11 is the latest version of the analogue and mixed-signal design software for IC, MEMS and optical design from Tanner EDA
In-system programmable PLD runs to 1024 macrocells
(August 2003)
Lattice Semiconductor has added of two new devices to its revolutionary in-system programmable expanded PLD family, the ispXPLD 51024MX and ispXPLD 5256MX devices
C synthesis joins FPGA design flow
(May 2003)
The latest version of Aldec Active-HDL now supports C synthesis through its interface with Celoxica's DK2 Design Suite
Design suite supports latest platform FPGAs
(May 2003)
Celoxica is supporting the 90nm Spartan-3 series of FPGAs from Xilinx with its DK Design Suite, providing designers with a C-based language design environment for platform FPGAs
Hardware acceleration speeds through simulation
(May 2003)
Riviera-IPT is a unified, assertion-based hardware acceleration platform that maximises simulation performance and accelerates ASIC and FPGA design verification by 10-50x over traditional methods
Cores turn FPGAs to PowerPC interfacing
(May 2003)
Eureka Technology has optimised three PowerPC interface IP cores for use with Actel's nonvolatile ProASIC Plus, Axcelerator, SX-A and RTSX-S FPGAs
Programmable designs keep track of revisions
(February 2003)
Lattice Semiconductor has released a powerful new generation of its ispLever design tool suite
In-system programmable devices come to handhelds
(January 2003)
Lattice Semiconductor reckons its 1.8V ispMACH 4000Z CPLD family that sets a new standard for the industry's lowest static power consumption
Programmable logic stretches to automotive specs
(September 2002)
The ispMACH 4000V family from Lattice Semiconductor now supports the full automotive ambient temperature range of -40 to +125C
Design software explained in Sophia
(September 2002)
Celoxica is both exhibiting and presenting a paper at SAME 2002 (Sophia Antipolis Forum on Microelectronics) from 9th to 10th October
Novel PLD trades logic and memory functions
(July 2002)
The ispXPLD (in-system programmable expanded PLD) architecture is the first PLD architecture to allows users to efficiently trade-off fast logic and block memory resources
Complex logic range goes even wider
(June 2002)
Lattice Semiconductor has released the first member of its 2.5V ispMACH 5000B family, the 256-macrocell ispMACH 5256B