Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Functional verification",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Language link eases verification from
OneSpin Solutions, which we summarised at the time by saying "OneSpin's 360 MV ensures that all functional errors in complex digital modules and intellectual property (IP) are detected".
The day before,
we featured the news release EDA tools standardise on Unified Power Format from
Synopsys: "Standard enables users to create a consistent description of the low power design intent for use by EDA tools for design and verification of today's low power ICs".
In November 2007, we covered the news from Cadence Design Systems
concerning its Incisive
- take a look at Verification plan speeds overall development
which says: "Micronas has selected the Cadence Incisive Plan-to-Closure Methodology and Incisive Enterprise Manager for verification planning".
Take a look also at the news release from Synopsys, Verification systems handle complex SoCs,
as well as Verification kit eases design process from Cadence Design Systems,
and Verification library receives approval from Accellera.
See also:
Collaboration to improve ASIC verification
(May 2007)
Synopsys and Synplicity have agreed to work together on next-generation high-performance verification solutions for ASIC designers
ASIC verification nears full device speed
(May 2007)
Software offers full visibility into FPGA-based ASIC and ASSP prototypes enabling designers to find, fix and verify functional errors at speeds approaching that of the final device
Functional verification expands in scope
(May 2007)
Platform addresses low-power verification and incorporates verification management capabilities that enable closed-loop management reporting, analysis and documentation
Graphical approach eases complex verification
(May 2007)
Graph based functional test synthesis tool helps users to understand, define and analyse complicated verification requirements
Kit cuts the cost of low-power IC design
(May 2007)
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort
Board sets the standard in verification
(May 2007)
The Accellera Board of Directors has approved the SCE-MI 2.0 specification as an Accellera verification standard
Verification IP automates manual register checks
(April 2007)
IP automates functional verification of configuration registers for system-on-chip designs
Triple approach verifies clock domain crossing
(April 2007)
All-new new approach to CDC verification is engineered to verify that data traversing asynchronous clock domains on ASIC, SoC or FPGA devices is received reliably
Verification IP chosen for the next generation
(April 2007)
JMicron Technology has chosen the PCI Express Gen2 nVS from nSys Design Systems to accelerate its next generation designs
Software verifies low-power features in new chips
(April 2007)
Software ensures compliance with the widely supported Unified Power Format (UPF) 1.0 Accellera standard
Three additional cards for VMM tester
(March 2007)
Three additional components to the VMM methodology, comprising VMM Planner, VMM Applications, and VMM Automation help development teams to define, measure and achieve verification objectives
Tools to verify complex mixed-signal chip designs
(March 2007)
Leading international chip companies make use of design verification software
Design software for programmable logic arrays
(February 2007)
Programmable logic and design software specialist team up on design tools for field programmable object arrays
ST leads European embedded project
(February 2007)
A strategic targeted research project aims to ensure that the European electronics industry continues to maintain its competitive position in embedded systems
Functional simulator is 40 to 80 times faster
(January 2007)
The new TurboXim fast functional simulator is 40 to 80 times faster than Tensilica's proven cycle-accurate ISS (instruction set simulator)
Functional verification speeds SuperHyway bus SoCs
(January 2007)
Renesas Technology Corp has adopted the VCS functional verification solution for the development of complex SoCs
Compiler generates RTL from untimed ANSI C
(January 2007)
C-to-RTL compiler works efficiently on large, complex designs at a high level of abstraction and then automates the process of creating high-performance hardware solutions
Wolfson signs for design, verification and IP
(November 2006)
Wolfson Microelectronics has selected Synopsys' Galaxy Design and Discovery Verification Platforms for the design and verification of its analogue mixed-signal ICs
Freescale signs for verification support
(November 2006)
Freescale Semiconductor and Synopsys have signed an agreement for Freescale's use of Synopsys electronic design automation software for the functional verification of complex semiconductor designs
Prototyping platforms put FPGAs in avionics
(November 2006)
Actel has partnered with Aldec to offer two highly integrated solutions designed specifically for FPGAs in high-reliability avionics and aerospace applications
Cosimulation link aids functional verification
(November 2006)
Link for Cadence Incisive integrates Matlab and Simulink with the Incisive functional verification platform for efficient design and verification of SoCs, ASICs and FPGAs
Teamwork software unifies concurrent design
(October 2006)
The Cadence Logic Design Team Solution allows concurrent RTL design, enabling schedule predictability
Testbench doubles verification productivity
(October 2006)
Enterasys Networks has selected the Synopsys VCS functional verification solution and its SystemVerilog Native Testbench following an extensive evaluation of available solutions
Verification IP covers OCP-based SoCs
(September 2006)
Verification IP for the OCP interface responds to customer demand for using the DesignWare Library and VCS Verification Library to verify systems and cores that use OCP
Emulation system runs extremely quickly
(September 2006)
Xtreme III Systems represent the next generation of the Incisive Xtreme series of accelerator/emulators within the Incisive functional verification platform
Platform promises faster route to custom SoCs
(September 2006)
Custom design platform for advanced analogue, mixed-signal, RF and custom digital design addresses challenges across a wide range of process nodes and design styles
Realtek finds critical bugs in power connections
(August 2006)
Realtek, a leading IC design house in Taiwan, uses Encounter Conformal Low Power and Encounter Conformal Constraint Designer to significantly reduce verification risks
Analog fastspice and RF fastspice tools
(July 2006)
Tools deliver Full-Spice Accuracy at 5x-10x Performance Without Tuning
Multi-year OEM agreement with Eve
(July 2006)
Synplicity has signed a multi-year OEM agreement with Eve pursuant to which Synplicity will provide Eve's customers with access to Synplicity's industry-leading FPGA synthesis technology
Simulation platform integrates speedy Spice
(July 2006)
Mentor Graphics Integrates the Newly Acquired ADiT Fast-SPICE Technology with ADVance MS
Estrada takes charge of operations
(July 2006)
Berkeley Design Automation has appointed Paul Estrada as Chief Operating Officer
News on the Functional Verification Kit for ARM technology from Cadence Design Systems
(June 2006)
The Cadence Functional Verification Kit for ARM technology, presenting design teams with a low-risk path to verification closure when verifying ARM processor-based designs
Programme helps Wavion to first silicon success
(June 2006)
Tower Semiconductor has begun production of the IC00100 metro Wi-Fi baseband controller for Wavion, a developer and supplier of a new generation of metro Wi-Fi systems for the communications industry
Functional verification moves to next generation
(May 2006)
The Questa verification solution combines tools, methodology and industry partners to deliver a new level of verification productivity and efficiency to today's designers