Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Hardware verification",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Optical interfaces boast top bandwidth from
Xilinx, which we summarised at the time by saying "FPGA-based designs accelerate the design cycle of wired networking systems that require OC-192 (10Gbit/s), multiple OC-48 (2.5Gbit/s) or 10Gbit/s Ethernet interfaces".
A few weeks before,
we featured the news release Critical controller boards put on trial from
XJTAG: "System provides a comprehensive set of tools to test, debug and program complex printed circuits containing ball grid array devices".
In October 2007, we covered the news from Altera Europe
concerning its Quartus II Version 7.2
- take a look at Software speeds compiling
which says: "A Quartus II software user working with a multiprocessor computer will experience, on average, a 20% reduction in compile times over single-processor computers".
Take a look also at the news release from CoWare, Model sets enable hardware verification,
as well as Hardware verification precedes boundary scan tests from Goepel Electronic,
and Verification IP automates manual register checks from Denali Software.
See also:
Boost for debug visibility and productivity
(January 2007)
TotalRecall technology allows access to debug visibility that meets or exceeds that of an emulator, while running at speeds of 10x to 100x faster
Predictable software, hardware and system quality
(December 2006)
Automated hardware, embedded software and system-level verification with system-wide management and new high-performance engines
Development platform puts PCI Express IP on trial
(September 2006)
Evaluation and development platform is designed for Synopsys' DesignWare PCI Express IP
Mathworks introduces link for modelsim 2
(July 2006)
Tool upgrade adds direct verilog support; collaboration with Mentor Graphics, streamlines verification process and enhances model-based design
Writing testbenches using SystemVerilog
(April 2006)
A new book aims to help design engineers learn advanced verification techniques using the SystemVerilog IEEE1800-2005 standard language
Software verifies processor-based board designs
(February 2005)
Kozio is a US company that delivers a complete diagnostics and functional test platform that efficiently accelerates the development of new processor based board designs
Hardware design in an SoC world
(July 2004)
Adopting a virtual-prototype-based SoC development process offers all-round benefits, and makes the hardware designer's job easier, argues Graham Hellestrand, founder of Vast Systems Technology
Package accelerates verification regression
(April 2004)
New enhancements to DesignPlayer will allow it to be seamlessly plugged into hardware regression environments, be driven by a variety of testbenches, and provide a 10x or greater performance gain
Verification accelerator supports System C
(April 2004)
An updated version of the VStation TBX verification accelerator delivers full support for the leading system design languages
Cosimulation tool scoops EDN award
(April 2004)
The MathWorks software tool Link for ModelSim has won the EDN Innovation of the Year Award in the EDA: Design Exploration category
Investors queue up to follow Carbon
(January 2004)
Carbon Design Systems has raised a $10 million series B second round of funding in just 90 days
EDA veteran Arnout comes onboard
(December 2003)
Elixent has appointed Dr Guido Arnout as a Nonexecutive Director
FPGA platform speeds PCI Express development
(October 2003)
A new flexible development solution supports a variety of uses in the development, prototyping and verification of PCI Express-based systems in FPGAs
Alliance aims for system-to-silicon solution
(September 2003)
Cadence Design Systems and CoWare have formed a strategic alliance to accelerate time to market for SoC design teams through a standards-based system-to-silicon-design solution
Axis aids in integrated verification flow
(August 2003)
Axis Systems and ARM have signed an agreement to develop a fully integrated, system-level verification flow for ARM cores and the ARM PrimeXsys Platform
'Zero-bugs' system turns to software development
(August 2003)
ZeBu-IP is a companion version to EVE's powerful 'zero bugs' hardware verification system designed to accelerate the development cycle for embedded software designs
Integration aims to speed verification
(July 2003)
Tharas Systems has joined Verisity's Interoperability Partners (VIP) programme to develop an integration between its Hammer hardware accelerator and Verisity's eCelerator testbench acceleration tool
Aptix alliance to provide hardware acceleration
(July 2003)
Aptix is to integrate its System Explorer hardware accelerator with Verisity's eCelerator testbench acceleration tool
Multiboard emulator scales up to bigger challenges
(May 2003)
A novel advanced, multiboard hardware verification system extends the capacity of designs from 1.5 million to 12 million ASIC-equivalent gates
ARM deal extended for five years
(March 2003)
Cadence and ARM have signed a new five-year agreement targeting design chain optimisation for their mutual customers
Open software advances EDA interoperability
(October 2002)
Synopsys has released its Switching Activity Interchange Format as an open source format together with an open source parser for the OpenVera hardware verification language
Vera speeds verification of Sonet/SDH chip
(September 2002)
NEC Electron Devices has successfully verified its latest Sonet/SDH framer physical layer chip with Synopsys' Vera testbench automation tool
Hardware verification takes on new Intel spec
(April 2002)
Synopsys has released OpenVera 2.0, with new additions to OpenVera assertions based on Intel's ForSpec language
Emulator links with testbench accelerator
(March 2002)
IKOS Systems has created a transaction-based integration to Verisity's eCelerator
The art of verification with VERA
(September 2001)
Verification Central and Synopsys have jointly launched a new book: 'The art of verification with VERA', by Faisal Haque, Khizar Khan and Jonathan Michelson
Platform accelerates SoC design and verification
(August 2001)
Mentor Graphics describes its Platform Express environment as the semiconductor design industry's first for rapidly creating, configuring and verifying platform-based, SoC designs