Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "HDL design",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Design companies agree on verification from
Mentor Graphics UK, which we summarised at the time by saying "The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability".
A few weeks before,
we featured the news release Programmable logic design suite is free to use from
Lattice Semiconductor UK: "ispLever Classic is a comprehensive software design tool suite that supports all mature Lattice programmable devices".
In November 2006, we covered the news from HDL Works
concerning its HDL Companion
- take a look at Navigation environment for HDL designs
which says: "Re-using existing code (legacy or third party) is becoming everyday practice to get designs done within schedule".
Take a look also at the news release from Mentor Graphics UK, Functional verification moves to next generation,
as well as Editing environment makes sense of HDL code from HDL Works,
and Simulation capability for DSP designers from Altera Europe.
See also:
HDL design suite gains its own spellchecker
(October 2005)
Mentor Graphics has developed a novel concurrent design checking and creation environment, which is available in the latest version of the HDL Designer Series tool suite
Design entry tool is optimised for Actel IDE
(July 2005)
HDL Works has joined Actel's EDA Alliance Programme and has developed a version of its Ease design entry tool optimised for Actel's Libero integrated design environment design flow
Software optimises the edit-compile-debug cycle
(June 2005)
HDL Works has released a new version of Ease, the graphical HDL design entry environment
HTML approach speeds HDL debug
(March 2005)
Available now from HDL Works is version 1.2 of HDL Companion, the HDL analysis, navigation and editing environment
Free tools to start on programmable logic design
(February 2005)
Lattice Semiconductor has released Version 4.2 of its web-downloadable ispLever-Starter programmable logic design tool suite
Software does the lot for Actel FPGAs
(December 2004)
Aldec has released a special Actel Edition of Active-HDL 6.3, offering easy-to-use pushbutton integration with Actel's Designer series advanced place-and-route software
Tool suite boasts faster FPGA design
(November 2004)
The latest release of the ispLever programmable logic design tool suite offers a comprehensive upgrade and enhancement in performance and functionality
Software speeds Stratix II designs
(March 2004)
Aldec now supports Altera's latest high-density Stratix II FPGA device family with its graphical design entry tool, Design Flow Manager, as well as its mixed-VHDL and Verilog simulator
FPGA software improves Xilinx quality of results
(February 2004)
Synplicity has enhanced its FPGA synthesis and physical synthesis software to provide optimised support for the latest version of Xilinx's Integrated Software Environment (ISE)
More speed and features for HDL designers
(January 2004)
In addition to a twofold performance increase over the previous version, Active-HDL 6.2 includes an improved advanced dataflow, library encryption, branch coverage and X-Trace
Free evaluation for HDL software
(November 2003)
HDL Companion is an ideal environment for developing, understanding and maintaining complex HDL designs and facilitates re-use of internally and externally developed IP
Coverification speeds soft-core FPGA designs
(September 2003)
CoVer is a novel hardware/software coverification platform for FPGA designs using soft-core microprocessors
Tool simplifies FPGA/DSP infrastructure
(July 2003)
Dimetalk is a novel tool for the rapid creation and modification of the communications infrastructure for FPGA-based DSP systems
FPGA software moves to a new level
(July 2003)
The latest version of FPGA Advantage features a new design cockpit that integrates recent updates to the HDL Designer Series, ModelSim and Precision RTL Synthesis products
Rule set enforces IP re-use guidelines
(November 2002)
SpyGlass Predictive Analyzer now includes the new STARC policy, an extensive set of analyses based on the widely used HDL Design Style Guide by HD Lab
Speedy support for Cyclone FPGAs
(September 2002)
The Mentor Graphics ModelSim simulation and LeonardoSpectrum synthesis design tools will be among the first to support Altera's new Cyclone FPGA device family
Software helps in Verilog training course
(August 2002)
Special editions of the Mentor Graphics ModelSim simulator and LeonardoSpectrum synthesis tools are to be included in a new self-study programme for learning PLD design and Verilog
Infinitely reconfigurable FPGAs are instantly on
(July 2002)
The ispXPGA (in-system programmable expanded programmable gate array) family combines on-chip E2 memory with SRAM cells in a nonvolatile architecture that allows infinite reconfiguration
New advantage to multivendor FPGA design flow
(July 2002)
FPGA Advantage 5.3 is the latest version of the industry-leading HDL design flow for managing the creation, simulation and synthesis of field-programmable gate array devices
Full support package for Axcelerator FPGAs
(July 2002)
Mentor Graphics is providing complete front-end design support for the new Actel Axcelerator family
Award recognises EDA interoperability efforts
(June 2002)
Synopsys has presented Mentor Graphics with the second annual Tenzing Norgay EDA Interoperability Achievement Award
Conference proceedings cover language-based design
(May 2002)
The proceedings of this year's International HDL Conference (HDLCon) are now available for purchase from Accellera
Synthesis demo by video-on-demand
(April 2002)
Mentor Graphics will showcase the new Precision Synthesis platform today at Programmable World 2002
Design flow speeds programmable SoC solutions
(April 2002)
Mentor Graphics and Atmel have developed a comprehensive design flow for Atmel's award winning programmable SoC solutions
Design tool support extends to latest FPGAs
(March 2002)
Mentor Graphics has released comprehensive design tool support for the new Virtex-II Pro FPGA family from Xilinx
Enhancement speeds prototyping and verification
(February 2002)
C-Bridge technology is an extension to the Mentor Graphics Seamless coverification environment
FPGA prototyping speeds SoC verification
(February 2002)
SpeedGate DSV (Direct System Verification) is an advanced verification environment for creating ASIC and SoC prototypes using off-the-shelf FPGAs
FPGA software imports legacy designs with ease
(November 2001)
FPGA Advantage 5.2 from Mentor Graphics provides designers with an integrated environment for design creation, management, simulation and synthesis of FPGAs
Mentor joins Open System C Initiative
(October 2001)
Mentor Graphics has joined the Open System C Initiative as a corporate member
Mentor has designs on student bodies
(October 2001)
Mentor Graphics has announced the details of its 2001-2002 Higher Education Programme student design contest, cosponsored by Sun Microsystems