Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Nanometre designs",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Software slashes nanometre design times from
Synopsys, which we summarised at the time by saying "The 2007.12 release Synopsys' PrimeTime suite has managed an average 2X runtime improvement and 33% memory reduction over the 2006.12 release".
Several months prior to that,
we featured the news release Clock tree synthesis passes nanometre GPU test from
Azuro: "Successful evaluation demonstrates PowerCentric's ability to reduce power and also meet complex variability-driven clock tree implementation requirements".
In May 2007, we covered the news from Azuro
concerning its PowerCentric
- take a look at Clock tree synthesis and optimisation unite
which says: "PowerCentric brings together unique algorithms for clock tree buffering, gate-level clock gate logic synthesis and statistical average-case dynamic power analysis".
Take a look also at the news release from Synopsys, Analogue and mixed signal verification for SOCs,
as well as Next-generation OPC solution from Mentor Graphics from Mentor Graphics UK,
and IDM is impressed with speed and accuracy from Nanno Solutions.
See also:
Distributors cover Japan, Korea and Taiwan
(October 2006)
Distributor agreements with Ivis, Seloco and Avant Technology award exclusive distributor rights in Japan, Korea and Taiwan, respectively
Design-for-test tool runs at-speed
(October 2006)
LogicVision has unveiled its ScanBurst tool and has partnered with Mentor Graphics to deliver a unique and improved at-speed test solution for high-speed nanometre designs
Scan compression automation proves popular
(July 2006)
DFT MAX scan compression automation solution has been instrumental in reducing test costs related to data inflation on more than 50 successful tapeouts since its general release in September 2005
Timing analyser handles 20-million-gate designs
(July 2006)
NEC Electronics' EMMA project team has successfully taped out designs with up to 20 million gates using Incentia's TimeCraft static timing analyser and its advanced on-chip-variation analysis
Embedded tests enhance memory reliability
(June 2006)
LogicVision and Dolphin Technology have developed an integrated and comprehensive self-testable and self-repairable memory solution for advanced nanometre designs
Software upgrades static timing analysis
(April 2006)
TimeCraft software has an advanced on-chip-variation capability for improving the accuracy and efficiency of static timing analysis for 90 and 65nm designs
Hybrid optimisation resolves ASIC design conflicts
(March 2006)
Software automates standard cell design optimisation for timing, area and leakage power, accelerating design closure for high-speed standard cell designs
Software helps designers perform power analysis
(December 2005)
Using Synopsys' Composite Current Source modelling technology, designers are, for the first time, able to perform comprehensive timing, noise and power analysis using a single, open library model
Kawasaki Micro maximizes delay test coverage
(November 2005)
Kawasaki Microelectronics has selected Cadence Encounter True-Time technology, the delay test ATPG that uses design timing to automatically generate faster-than-at-speed delay tests
Encounter Test family validated on Agilent's 93000
(November 2005)
The Cadence Encounter Test family of products has been validated on Agilent's 93000 SOC Series automated test system
Diagnostic tool enhances semiconductor yield
(November 2005)
Mentor Graphics' YieldAssist diagnostic tool enhances semiconductor yield and expands the firm's Design-for-Test product portfolio and platform beyond classical test generation and defect detection
Novel tool cuts GDSII data down to size
(October 2005)
SoftJin Technologies reckons its new design tool GDSIIZIP compresses large IC layout files in GDSII format by up to 20 times, making it four or five times better than existing products
Compiler synthesis proves popular in Japan
(July 2005)
Canon has adopted Encounter RTL Compiler for its ASIC designs, further increasing momentum of RTL Compiler synthesis in Japan
RTL compiler speeds LCD controller to tapeout
(July 2005)
Seiko Epson Corp of Japan has doubled productivity in the production tapeout of a high-volume LCD controller chip using Cadence Encounter RTL Compiler synthesis
Compiler speeds image processor to tape-out
(June 2005)
Nethra Imaging has successfully taped out its first product, the NI-2050 image processor designed for mobile handset applications, using Cadence Encounter RTL Compiler synthesis
Compiler helps cut nanometre designs down to size
(June 2005)
Essence Technology of Taiwan has achieved an important sample tapeout with Cadence Encounter RTL Compiler synthesis, part of the Encounter digital IC design platform
Models help depict first-order nanometre effects
(June 2005)
ARM, TMSC, Virage Logic and Library Technologies are all supporting Synopsys open source Liberty Composite Current Source models in their IP for semiconductor design
Scan test tool joins reference flow
(June 2005)
Taiwan Semiconductor Manufacturing Company (TSMC) has added the TestKompress scan test tool to its Reference Flow 6.0
IP platform optimised for UMC 130nm process
(May 2005)
ARM is to provide its Artisan Metro low-power IP platform for UMC's advanced 130nm process technology
RTL compiler delivers production-cost savings
(May 2005)
Ricoh Company has successfully taped out a 3-million-gate chip ahead of schedule and with reduced gate count using the Cadence Encounter digital IC design platform, including RTL Compiler synthesis
Wipro signs up for continued support
(March 2005)
Wipro Technologies has renewed an agreement under which Cadence provides it with access to its electronic design automation (EDA) technologies
S3 encounters multiple designs at 90nm
(February 2005)
The Cadence Encounter digital IC design platform has helped Silicon and Software Systems deliver multiple 90nm designs over the past 18 months
Compiler helps Sanyo reduce power consumption
(January 2005)
Sanyo has achieved an important production tapeout with the Cadence Encounter digital IC design platform, including RTL Compiler synthesis
Fujitsu encounters first-pass success 66 times
(January 2005)
Cadence Design Systems has helped Fujitsu to successfully achieve first-pass silicon on 66 consecutive designs
Embedded memory system addresses nanometre issues
(January 2005)
A leading provider of semiconductor IP platforms and pioneer in self-test and self-repair embedded memories, Virage Logic Corp
Novel tool promises to boost nanometre yields
(October 2004)
Cadence Encounter Diagnostics is billed as the semiconductor industry's first yield diagnostics tool
New engines improve nanometre parasitic extraction
(September 2004)
New resistance and capacitance engines for Calibre xRC enable the industry's most accurate simulation of nanometre technology
Parasitic extraction validated for 90nm process
(June 2004)
The Calibre xRC transistor-level parasitic extraction solution has been silicon validated by UMC for its 90nm process technology
Platforms join new TSMC flow
(June 2004)
Both the Encounter digital IC design platform and the Allegro system interconnect design platform have been integrated into TSMC's Reference Flow 5.0
Philips commits to Galaxy
(June 2004)
Royal Philips Electronics has signed a new multiyear volume purchase agreement extending and expanding its deployment of the Synopsys Galaxy front-end design platform
Timing delay tester tackles nanometre designs
(May 2004)
Cadence Design Systems reckons it has brought timing to the manufacturing floor with True-Time delay test for processes at 130nm and below
Software automates library cell creation
(May 2004)
ZenCell Factory is a novel automated library cell creation solution for standard cell-based design
Simtek adopts parasitic extraction solution
(May 2004)
Simtek Corp has adopted Calibre xRC, Mentor's parasitic extraction solution for nanometre design, for its high-performance nonvolatile memory designs
Faster timing closure for cell-based designs
(April 2004)
ZenTime 2.1 brings cell-based designers a three- to four-fold increase in run-time speed, allowing them to achieve timing closure on complex, high-speed, nanometre blocks in a matter of days