Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Parasitic extraction",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Parasitic extraction works on 45nm process from
Synopsys, which we summarised at the time by saying "Collaborative effort validates advanced modelling of key process variation effects that impact the performance of digital, analogue and memory circuits".
Several months prior to that,
we featured the news release ASIC company standardises on timing tools from
Synopsys: "Fujitsu standardises on tools for static timing analysis, delay calculation and interconnect parasitic extraction".
In January 2007, we covered the news from Synopsys
- take a look at Proposal enhances IEEE1481 SPEF standard
which says: "The IEEE1481 working group has approved Synopsys' proposal for an extension to the Standard Parasitic Exchange Format (SPEF) for process and temperature variation".
Take a look also at the news release from Mentor Graphics UK, TSMC-qualified process design kit,
as well as Wireless SoC reference flow bears fruit from Cadence Design Systems,
and Mentor Graphics Calibre nmDRC adopted by UMC from Mentor Graphics UK.
See also:
Synopsys primeyield LCC links to IC compiler
(July 2006)
Synopsys primeyield LCC links to IC compiler for automated correction of lithography problems
Design rule checker adapts to the nanometre era
(July 2006)
Calibre nmDRC redefines traditional design rule checking by dramatically reducing total cycle time and integrating critical elements such as critical area analysis and critical feature identification
Tools smooth the way from FPGAs to 65nm process
(May 2006)
Altera has deployed Synopsys' Star-RCXT extraction tool and HSIM FastSpice simulator for its FPGA design flow targeting TSMC's 65nm Nexsys process technology
Design for manufacturing tools support 65nm node
(May 2006)
A 65nm design support ecosystem channels design-for-manufacturing capabilities through selected electronic design automation tools directly to designers' workstations
Chinese designers adopt Galaxy
(April 2006)
Hisilicon Technologies has adopted Synopsys' Galaxy Design Platform as its primary IC design flow for 130nm designs
Software expands to custom design and verification
(March 2006)
Parallel Systems offers preselected Cadence customers a broader portfolio of Cadence products fully supported by Cadence's customer support group
ATI adds parasitic extraction tool
(March 2006)
ATI Technologies has deployed Synopsys' Star-RCXT extraction tool for its digital design flows
Encryption secures process design kits
(December 2005)
IBM has adopted patent pending Calibre encryption technology for use with its 90, 65 and 45nm process design kits
Kit addresses key challenges in wireless design
(December 2005)
The Cadence RF Design Methodology Kit helps wireless chip designers achieve shorter, more predictable design cycles by better ensuring that silicon performance matches design intent
Marvell goes from RTL to GDSII
(October 2005)
Marvell has adopted Synopsys' Galaxy Design Platform as a RTL-to-GDSII design solution to develop networking and storage products
Verification system optimised for rapid turnaround
(September 2005)
The Cadence Physical Verification System is optimised for rapid turnaround of design rule check and layout versus schematic
Parasitic extraction tool upgraded
(September 2005)
Q3D Extractor computes 3D RLC/2D RLCG parameters from interconnect structures and automatically generates an equivalent Spice circuit
Verification and extraction tools integrated
(August 2005)
Mentor Graphics' Calibre physical verification and extraction tools are now fully integrated into the Cadence design creation environment
Package design links with 3D EM simulation
(July 2005)
Turbo Package Analyzer combines new bidirectional integration with Synopsys' Encore package-design software with Ansoft's state-of-the-art 3D electromagnetic simulation
Platform helps meet wireless SoC yield goals
(June 2005)
Renesas Technology Corp has taped out a 90nm SoC design for wireless applications using Synopsys' Galaxy Design Platform
Graphics processor shows off X Architecture
(June 2005)
ATI Technologies, Cadence Design Systems and TSMC have successfully produced the foundry industry's first X Architecture device
Reference flow to speed complex designs
(December 2004)
Sasken has used the Synopsys Galaxy design platform to develop a reference flow to enhance the implementation and signoff process for its complex designs
New engines improve nanometre parasitic extraction
(September 2004)
New resistance and capacitance engines for Calibre xRC enable the industry's most accurate simulation of nanometre technology
Renesas standardises on signoff solution
(July 2004)
Renesas Technology Corp has standardised on Synopsys' Star-RCXT for resistive-capacitive (RC) parasitic extraction in its design flow
New flow speeds 62-million-transistor to tape-out
(July 2004)
Cadence has provided a complete back-end design flow for one of Motorola's most complex chips, incorporating more than 62 million transistors
Design kit supports SMIC mixed-signal process
(July 2004)
Mentor Graphics has released a technology design kit (TDK) for Semiconductor Manufacturing International Corp's 0.18um mixed-signal process technology
Parasitic extraction validated for 90nm process
(June 2004)
The Calibre xRC transistor-level parasitic extraction solution has been silicon validated by UMC for its 90nm process technology
Platforms join new TSMC flow
(June 2004)
Both the Encounter digital IC design platform and the Allegro system interconnect design platform have been integrated into TSMC's Reference Flow 5.0
Collaboration marries IC and package design
(June 2004)
Ansoft is working with Synopsys to provide streamlined IC and package codesign and analysis design flow solutions
Platform approved for IBM-Chartered process
(May 2004)
The Calibre design-to-silicon platform has been named as an approved physical verification tool for the 90nm semiconductor process platform jointly developed by IBM and Chartered Semiconductor
Simtek adopts parasitic extraction solution
(May 2004)
Simtek Corp has adopted Calibre xRC, Mentor's parasitic extraction solution for nanometre design, for its high-performance nonvolatile memory designs
Platform integrated with OpenAccess database
(May 2004)
The Mentor Graphics Calibre design-to-silicon platform is now integrated with the OpenAccess database
Toshiba tapes out multiple 90nm SoC designs
(April 2004)
Toshiba Corp has taped out multiple 90nm SoC designs for its audiovisual and office equipment product lines using the Synopsys Galaxy design platform
Parasitic extraction package validated
(April 2004)
Star-RCXT - the industry standard for RC parasitic extraction - has been validated for UMC's most advanced 90nm processes
Parasitic extraction solution verified for TSMC
(March 2004)
TSMC has verified Star-RCXT - a key product in Synopsys' Galaxy design platform and standard in the TSMC Reference Flow
Synthesis solution includes on-chip passives
(March 2004)
Q3D Extractor v6 is Ansoft's next generation of 3D parasitic extraction technology
Signal integrity tool solves IC package parasitics
(December 2003)
Developed to address signal integrity issues in today's high-speed IC package designs, Icemax provides substrate designers and electrical analysts with a simple highly automated modelling environment
Verification platform gains mixed-signal simulator
(September 2003)
Discovery AMS is a new and comprehensive simulation solution claimed to deliver significant productivity improvements for analogue and mixed-signal verification
Alliance to aid nanometre design
(September 2003)
Mentor Graphics has joined the Chartered Semiconductor NanoAccess Alliance