Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Parasitics",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Software slashes nanometre design times from
Synopsys, which we summarised at the time by saying "The 2007.12 release Synopsys' PrimeTime suite has managed an average 2X runtime improvement and 33% memory reduction over the 2006.12 release".
A couple of weeks before,
we featured the news release Dual operating modes boost controller flexibility from
STMicroelectronics: "The L6566 selectable multimode controller is suitable for applications such as flyback AC/DC adapters, TV and LCD monitors, small size LCD TVs, high end chargers and other consumer equipment".
In September 2007, we covered the news from Synopsys
concerning its DesignWare USB 2.0 nanoPHY
- take a look at US systems receive new certification
which says: "The DesignWare PHY IP for PCI Express offers a number of dedicated lane configurations from x1 to x8 that support both wire bond and flip chip packages".
Take a look also at the news release from Cadence Design Systems, IC platform cuts design times,
as well as EM simulator spreads coverage from Ansoft Europe,
and Software extends focus to IC-package codesign from Apache Design Solutions.
See also:
EDA tools target complexity at 65nm and below
(May 2007)
Upgraded netlist reduction and interconnect analysis tools help IC designers to optimise post-layout simulations, to maintain verification accuracy and to meet time to market goals
Chip layout tool adds 3D RC extraction
(April 2007)
Tool reduces design errors and shortens the design verification process, particularly for deep submicron technologies where interconnect delays start to play a dominant role
Camposano to spearhead growth phase
(April 2007)
Dr Raul Camposano has been named Chief Executive Officer at Xoomsys
Analogue and mixed signal verification for SOCs
(April 2007)
An integrated analogue and mixed-signal verification tool for system-on-chip designs comprises FastSpice simulation, unified debug and visualisation, and tight integration with digital verification
Coupler improves power amplifier gain control
(April 2007)
High-directivity coupler is designed to improve power amplifier gain control in various wireless systems including cellular and WiMAX system transmitters
Analogue simulator handles larger volumes of data
(March 2007)
New tool suite will feature a 3D RF extraction tool that uses a field solver technique to calculate interconnect parasitics in three dimensions
SpiceCheck does netlist debugging and verification
(February 2007)
SpiceCheck is an analysis, verification, and debugging (AVAD) suite for analogue and mixed-signal designers
Proposal enhances IEEE1481 SPEF standard
(January 2007)
The IEEE1481 working group has approved Synopsys' proposal for an extension to the Standard Parasitic Exchange Format (SPEF) for process and temperature variation
Cypress deploys Synopsys PrimeRail
(December 2006)
Synopsys has announced that Cypress Semiconductor has successfully taped out its West Bridge Antioch peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC)
DFM solutions come to market
(November 2006)
Clear Shape Technologies has formally introduced itself as a design-for-manufacturing solutions provider
Inductors promise high frequency performance
(November 2006)
Tight tolerance L0402 LGA inductor is based on thin-film technology, providing excellent high frequency performance and rugged construction for reliable automatic assembly
Webcast to discuss power PCB layout
(September 2006)
Webcast for designers covers 'PCB layout techniques for switching regulators'
Jivaro qualified for post layout simulation flow
(July 2006)
Edxact announces that STMicroelectronics has added Edxact's Jivaro parasitic reduction tools to its Post Layout Simulation flow (PLS), in order to speed up simulations of back-annotated netlists
Netlist-driven rule checker is fully programmable
(July 2006)
SpiceCheck performs netlist debugging from syntax verification to circuit-aware static checking and allows SoC designers to perform a global check on traditionally difficult-to-find design issues
Resistors and capacitors come together
(May 2006)
A resistor-capacitor network provides comms system designers with economical and space-saving termination for high speed memory buses and decoupling for high frequency data line drivers
Tools smooth the way from FPGAs to 65nm process
(May 2006)
Altera has deployed Synopsys' Star-RCXT extraction tool and HSIM FastSpice simulator for its FPGA design flow targeting TSMC's 65nm Nexsys process technology
ATI adds parasitic extraction tool
(March 2006)
ATI Technologies has deployed Synopsys' Star-RCXT extraction tool for its digital design flows
PWM control IC takes drivers onboard
(January 2006)
International Rectifier has launched a three-phase PWM control IC with integrated drivers for DC/DC convertors
Verification and extraction tools integrated
(August 2005)
Mentor Graphics' Calibre physical verification and extraction tools are now fully integrated into the Cadence design creation environment
Package design links with 3D EM simulation
(July 2005)
Turbo Package Analyzer combines new bidirectional integration with Synopsys' Encore package-design software with Ansoft's state-of-the-art 3D electromagnetic simulation
New devices shrink power management
(July 2005)
PolarFab has added a new family of devices to enhance its BP30 process
Models help depict first-order nanometre effects
(June 2005)
ARM, TMSC, Virage Logic and Library Technologies are all supporting Synopsys open source Liberty Composite Current Source models in their IP for semiconductor design
TSMC integrates nanometre design platforms
(June 2005)
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's latest reference flow
Wafer-level packaging shrinks SoC designs
(May 2005)
LSI Logic Corporation has released its enhanced wafer-level packaging (WLP) technology for use in ASIC/SoC designs
New process enables industrial amp advances
(May 2005)
Analog Devices is introducing a suite of amplifiers designed to meet the demanding signal conditioning requirements of high-voltage industrial and instrumentation equipment
Convertor module simplifies PSU design
(May 2005)
The iPOWIR iP1203 is a fully optimised full-function 15A single-output synchronous buck convertor device that achieves over 90% efficiency at full load
Halford to resolve signal integrity issues
(April 2005)
Advanced Layout Solutions has recruited Chris Halford to help support customers who are finding that signal integrity is increasingly becoming a concern within their PCB designs
Powertrain doubles DC/DC convertor density
(March 2005)
The Philips Intelligent Power 212-12M is billed as the industry's most advanced integrated powertrain that combines two power MOSFET switches and a driver IC into a single 8 x 8mm QFN package
Software offers thermal validation for IC packages
(February 2005)
Icechip is novel package-level thermal validation software for IC package designers
Design flow addresses to wireless challenges
(January 2005)
New software aims to give wireless chip designers and manufacturers better insight into the mixed-signal and radio frequency challenges that significantly impact wireless design
Upgrade for mixed signal process and libraries
(December 2004)
PolarFab has improved its 6in complementary BiCMOS (c-BiCMOS) RFBC/ABC3 processes to provide reduced die sizes and decreased design times
BiCMOS processes gain laser-trimmable resistors
(September 2004)
A new SiChrome (SiCr) thin film resistor that features low parasitics and a 500ohm sheet resistance to help reduce die size
New engines improve nanometre parasitic extraction
(September 2004)
New resistance and capacitance engines for Calibre xRC enable the industry's most accurate simulation of nanometre technology
Renesas standardises on signoff solution
(July 2004)
Renesas Technology Corp has standardised on Synopsys' Star-RCXT for resistive-capacitive (RC) parasitic extraction in its design flow