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‘Parasitics’

An Electronicstalk guide

Start with the news release Synopsys IP cores pass compliance testing from Synopsys, which we summarised at the time by saying "Synopsys has announced that the Designware USB 2.0 NanoPHY IP and PCI Express 1.1 PHY are the first internet protocol (IP) cores to achieve compliance in UMC's 65nm SP and LL process technologies.". Several months prior to that, we featured the news release MS4640A covers frequencies of 70 kHz to 70 GHz from Anritsu (UK): "Anritsu has introduced the Vectorstar premium series of microwave vector network analyzers (VNAs).".
 
In June 2008, we covered the news from Cadence Design Systems - take a look at Advanced simulator maintains Spice accuracy which says: "National Semiconductor is using the Spectre simulator to verify its large, complex production analogue ICs.".
 
Take a look also at the news release from Avago Technologies, Chip-scale packaging first for RF amplifiers, as well as IC design offering eases 65nm processes from Cadence Design Systems, and Circuit simulator receives upgrade from Cadence Design Systems.
 

Latest stories...
USB2.0 IP receives PHY certification (April 2008)

Synopsys' DesignWare USB 2.0 nanoPHY uses half the power and die area of previous USB PHY IP solutions and enables faster time to market with reduced risk.

IC design suite is improved all round (March 2008)

Significant upgrade to Tanner EDA's Windows-based tool suite for analogue and mixed-signal IC and MEMS design.

Software simulates electromagnetic fields (February 2008)

Engineers use Q3D Extractor to understand the performance of high-speed electronic designs and perform signal integrity analysis.

Software slashes nanometre design times (January 2008)

The 2007.12 release Synopsys' PrimeTime suite has managed an average 2X runtime improvement and 33% memory reduction over the 2006.12 release.

Dual operating modes boost controller flexibility (January 2008)

The L6566 selectable multimode controller is suitable for applications such as flyback AC/DC adapters, TV and LCD monitors, small size LCD TVs, high end chargers and other consumer equipment.

US systems receive new certification (September 2007)

The DesignWare PHY IP for PCI Express offers a number of dedicated lane configurations from x1 to x8 that support both wire bond and flip chip packages.

IC platform cuts design times (September 2007)

Cadence's new approach directly models critical elements of the manufacturing process instead of relying on conservative design rules.

EM simulator spreads coverage (July 2007)

Electromagnetic field simulator gains finite-element-based DC solver optimised for extraction of power rail geometry in complex low-voltage/high-current PCB and package designs.

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