Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Pattern generation",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Scan compression eases HDTV IC test regime from
Synopsys, which we summarised at the time by saying "DFT MAX automatically implements scan compression on-chip, which can reduce the amount of data required to test each manufactured part by 95% or more".
A few weeks before,
we featured the news release Acquisition unites test technologies from
Asset InterTech: "The complementary technologies of Asset and ITT furthers the convergence of Asset's JTAG-based structural test technology and ITT's functional testing capabilities".
In November 2007, we covered the news from Synopsys
concerning its UMC/Synopsys reference design flow
- take a look at Reference design flow eases chip evaluation
which says: "Synopsys' Design Compiler Ultra topographical synthesis engine enables engineers to accurately predict chip performance results during logic synthesis".
Take a look also at the news release from Synopsys, IC test generator takes power criteria onboard,
as well as Test module suits design companies from Synopsys,
and Technology improves testing accuracy from Synopsys.
See also:
Compression software expands Oki's test coverage
(January 2007)
Oki Electric has adopted the Synopsys DFT MAX scan compression automation solution to enable higher test quality for its digital designs
Tundra takes quick route to IEEE1149.6
(December 2006)
LogicVision's ETBoundary product provides a boundary scan solution for embedded test and diagnosis of integrated circuit pin functions and board-level interconnect
IBM signs up for 65nm ASIC support
(November 2006)
Cadence Design Systems has signed an agreement to incorporate Encounter RTL Compiler global synthesis and Encounter Test technologies into the IBM 65nm ASIC design kit
Reference methodology aids ARM-based design
(October 2006)
Cadence Design Systems is collaborating with ARM to expand the breadth of their joint reference methodology with the addition of Encounter Test timing and power-aware technology
Links accelerate IC yield ramp
(October 2006)
Links between TetraMAX automatic test pattern generation diagnostics and the Odyssey yield management system accelerate yield ramp at foundries
Design-for-test tool runs at-speed
(October 2006)
LogicVision has unveiled its ScanBurst tool and has partnered with Mentor Graphics to deliver a unique and improved at-speed test solution for high-speed nanometre designs
Tool interface spec is passed on to IEEE
(October 2006)
Accellera has approved a new test standard - the Open Compression Interface standard (OCI 1.0) - and its transfer to the IEEE for standardisation
Test pattern generator targets delay defects
(October 2006)
Automatic test pattern generation technology is designed to increase the quality of manufacturing tests by targeting small delay defects
Automatic test pattern generator accelerated
(September 2006)
Enhancements to the TetraMAX automatic test pattern generator result in a typical speedup of three times or more in runtime performance across all design styles
Octal ADC family runs up to 14bit resolution
(September 2006)
Eight-channel high-speed convertors are ideal for portable medical devices and ultrasound machines where lower power consumption and smaller board space are critical design considerations
Diagnostics technology lead extended
(July 2006)
Industry-award winning Cadence encounter test expands data compression and yield diagnostic offerings to address escalating manufacturing costs and yield ramp
Timing-aware test generation cuts design delays
(June 2006)
Comit Systems has standardised its automatic test pattern generation (ATPG) flow on Cadence Encounter Test
Quad 14bit ADC claims a first
(May 2006)
Analog Devices has released the industry's first high-speed 14bit data convertor with four analogue-to-digital conversion channels
Generators improve accuracy and control
(April 2006)
Pulse/pattern generators provide key performance advantages, such as superior signal quality and precise control for pulsewidths from 3ns to 1000s, as well as a simple, intuitive user interface
Cypress commits to design platform
(March 2006)
Cypress Semiconductor has signed a multiyear agreement to consolidate its digital IC design flows and methodologies using Synopsys' Galaxy Design Platform
Japanese consortium collaborates on test schemes
(January 2006)
Mentor Graphics has signed a joint development agreement with STARC, a research and development consortium cofounded by 11 major Japanese semiconductor companies
10Gbit/s transceiver cuts down on jitter
(January 2006)
The Si5040 leverages DSPLL technology to create the industry's first 10Gbit/s XFP transceiver IC with integrated jitter attenuating capability on both transmit and receive datapaths
DVD/CD SoC uses Encounter Test Architect
(November 2005)
Cadence Design Systems' Encounter Test Architect technology has helped Atmel successfully tape out its first single-chip DVD/CD system-on-chip (SoC)
ADCs improve image quality in ultrasound equipment
(September 2005)
Analog Devices is introducing a quad variable gain amplifier (VGA) and two quad analogue-to-digital convertors (ADCs) that dramatically improve image quality in advanced medical ultrasound equipment
Optical test and measurement at ECOC
(August 2005)
Yokogawa is featuring a number of new optical test and measurement products at ECOC 2005
Comprehensive testing for 10Gbit/s networks
(June 2005)
Yokogawa has introduced two compact, easy-to-use and economical instruments for 10Gbit/s bit-error-rate testing
New name in design-for-test market
(March 2005)
DeFacTo Technologies aims to leverage patent-pending DFT technology, develop products and services for the worldwide electronics market and become the leading provider of DFT tools
Pattern generators suit R and D and ATE
(February 2005)
The 72xx card family is billed as a unique system solution for universal pattern generation
ATPG starter packages improve ASIC quality
(October 2004)
The DFT-PRO 100 and 200 Series of automatic test program generator starter packages include the essential design-for-test tools for comprehensive ASIC testing
Novel tool promises to boost nanometre yields
(October 2004)
Cadence Encounter Diagnostics is billed as the semiconductor industry's first yield diagnostics tool
Software automates test generation
(October 2004)
Mentor Graphics has added new automated functionality to its FastScan automatic test pattern generation tool and its TestKompress embedded deterministic test tool
PC-based generators put logic devices to the test
(July 2004)
A series of pattern generation boards available in PCI, 6U CompactPCI and PXI formats offers the speed and power required for testing all today's high-speed logic devices
Design and verification for new 90nm process
(May 2004)
Synopsys Galaxy design and Discovery verification platforms have been verified for the new 90nm process platform common to both IBM and Chartered Semiconductor Manufacturing
Deep submicron designs stand the test of time
(April 2004)
The new releases of DFT Compiler and TetraMAX ATPG have improved design-for-test and automatic test pattern generation performance and pattern count for deep submicron designs
Acquisition range takes on demanding applications
(August 2003)
The Spectrum PCI ultra-high-speed board range is claimed to push forward the boundaries of PC-based data acquisition and waveform generation
Full SoC coverage from formal verification upgrade
(July 2003)
The latest release of Conformal provides a comprehensive solution that enables SoC designers and verification engineers to deliver functional bug-free silicon
Gateways bring JTAG testing onboard
(May 2003)
Two new JTAG gateway ICs enable design engineers to easily implement the IEEE1149.1 standard
Test solution aids core-based design development
(March 2003)
Synopsys has added a comprehensive test automation solution for core-based designs to its DFT Compiler, a key component of the Galaxy design platform
ATI signs for three-year support deal
(February 2003)
Mentor Graphics is to supply ATI Technologies with an integrated tool suite that will be used to verify its high-performance graphics processors and digital media silicon