Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Resolution enhancement",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Measurement link aids optical proximity correction from
Synopsys, which we summarised at the time by saying "Design for manufacturing interface helps customers to develop faster, more accurate and predictive OPC models for advanced 45nm and beyond technologies".
Earlier in the week,
we featured the news release Acquisition delivers powerful design-to-fab flow from
Mentor Graphics UK: "Mentor Graphics Corp has acquired Sierra Design Automation for US $90 million in cash and stock".
In February 2007, we covered the news from GenISys
- take a look at EVG and Genisys combine on lithography simulation
which says: "EV Group (EVG) has formed a collaborative product development partnership with Genisys for the development and marketing of a simulation platform for advanced mask aligner lithography processes".
Take a look also at the news release from ASML, Imaging, overlay and throughput improvements,
as well as Next-generation OPC solution from Mentor Graphics from Mentor Graphics UK,
and Cell BE processor to accelerate EDA from Mercury Computer Systems.
See also:
Compression algorithm cuts mask files down to size
(October 2006)
MEBESzip is a software product that compresses mask data files in MEBES format by a factor of 5-15x and significantly reduces file sizes as well as data transfer times
Design flow overcomes lithographic limitations
(October 2006)
Cadence Design Systems has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies with physical design and verification
Sematech seeks out next-generation lithography
(September 2006)
Sematech has awarded a contract to qualify the imaging performance of advanced logic patterns, metrology structures and defect designs for the 45, 32 and 22nm technology nodes
Design rule checker adapts to the nanometre era
(July 2006)
Calibre nmDRC redefines traditional design rule checking by dramatically reducing total cycle time and integrating critical elements such as critical area analysis and critical feature identification
TCAD tools run on dual-core processors
(June 2006)
A new Sentaurus TCAD release adds significant process and device modelling capabilities for accelerated development of advanced technologies
Software supports 65nm process introduction
(May 2006)
Cadence device and interconnect models, design flows and design for manufacturing technologies support Taiwan Semiconductor Manufacturing Company's 65nm technology
DFM software targets power leakages
(May 2006)
Blaze MO optimisation software is billed as the industry's first electrical DFM solution
Kailath joins the hall of fame
(February 2006)
Clear Shape Technologies cofounder Dr Thomas Kailath will be inducted into the Silicon Valley Engineering Council Hall of Fame on Friday 24th February 2006
Mask data toolsuite cuts files down to size
(February 2006)
TheCalibre MDP mask data preparation toolsuite has been qualified for production at leading IDMs for the 45nm process technology in flows based on OASIS, the next generation stream format
Suite makes IC designs more manufacturable
(February 2006)
The Cadence Virtuoso Resolution Enhancement Technology (RET) Suite integrates lithography awareness directly into the Cadence Virtuoso custom design platform
Verification software cuts costly mask respins
(January 2006)
Calibre OPCverify signals the beginning of a new generation of OPC technology, and expands the design for manufacturing (DFM) solutions from Mentor
Calibration library adds ion implantation data
(December 2005)
Synopsys has added Varian Semiconductor Equipment Associates' ion implantation process data to its Sentaurus calibration library
TCAD tools help explore new concepts
(October 2005)
The Sentaurus technology CAD tool suite embeds a comprehensive suite of core TCAD products for multidimensional process, device and system simulation into a powerful user interface
Verification system optimised for rapid turnaround
(September 2005)
The Cadence Physical Verification System is optimised for rapid turnaround of design rule check and layout versus schematic
Industry veterans join forces for DFM space
(November 2004)
Introducing DFM Challenger Aprio Technologies Industry veterans join forces to bring fresh ideas to DFM space
DFM technology runs on design-to-silicon platform
(October 2004)
Calibre Transition, Measure and Analyse are new features designed address critical design for manufacturing (DFM) requirements
Programme aims for photomask improvements
(September 2004)
Synopsys and Photronics have set up a joint programme to improve the manufacturability and quality of advanced photomasks and reducing the cycle times for design-to-photomask flows
Pair resolve to bridge software gap
(June 2004)
Cadence has signed a multiyear multi-million-dollar software licensing and joint development agreement with ASML MaskTools for advanced resolution enhancement technology software solutions
Upgrade for silicon-versus-layout verification
(May 2004)
Synopsys has made substantial enhancements to its SiVL silicon-versus-layout (SVL) verification tool - a key component of its design-for-manufacturing (DFM) solution
Alliance to aid nanometre design
(September 2003)
Mentor Graphics has joined the Chartered Semiconductor NanoAccess Alliance
Faraday uses xRC for parasitic extraction
(July 2003)
Faraday Technology is using the Mentor Graphics Calibre xRC product as its transistor level and GDSII-based gate level parasitic extraction tool for SoC designs
Tower joins the Calibre fan club
(June 2003)
Tower Semiconductor has selected Mentor's Calibre design-to-silicon platform as its internal manufacturing standard
Infineon sorts out nanometre designs
(June 2003)
Infineon Technologies has adopted the Mentor Calibre design-to-silicon platform, and the embedded deterministic test product, TestKompress, as key enablers for its nanometre IC design strategy
Parallel processing speeds nanometre design
(May 2003)
MTflex is an innovation in parallel processing for the Calibre design-to-silicon platform
Mask data preparation supports more formats
(April 2003)
Mentor has two new Calibre products, Calibre Fracturej and Calibre Fracturet, which support the JEOLV52 and Toshiba VSB11 mask writing machines
Higher resolution modelling to boost chip yields
(February 2003)
The latest significant enhancements to the Calibre suite of resolution enhancement technology (RET) tools effectively ensure Calibre's RET modelling accuracy for the next three technology nodes
Silterra standardises on Calibre
(February 2003)
Silterra Malaysia has selected Calibre as its internal standard for design rule checking, layout versus schematic and optical and process correction functionalities
Big two in EDA integration
(February 2003)
Mentor Graphics is to integrate its IC design products with the Milkyway design database from Synopsys
Early support for GDSII replacement
(October 2002)
Mentor Graphics is to support the as yet unnamed GDSII replacement format in its Calibre product family and the IC Station tool suite in commercial release as soon as the first quarter of 2003
Data preparation software aids mask accuracy
(March 2002)
Mentor Graphics has released the first software solutions in the Calibre mask data preparation (MDP) product line, the Calibre Fracturem and Calibre MDPview tools
Busy time for Mentor at SPIE conference
(February 2002)
Mentor Graphics will preview its new Calibre mask data preparation (MDP) technology and contribute 11 technical papers at the 27th annual SPIE Microlithography conference
Derrick takes Mentor to market
(January 2002)
Mentor Graphics has named Brian Derrick as the Vice President of Corporate Marketing
Verification extends to mask making
(October 2001)
Mentor Graphics has extended its Calibre technology to include the capability to export IC layout data directly into mask-writer formats
STMicroelectronics goes for subwavelength Calibre
(March 2001)
STMicroelectronics (ST) has adopted the Calibre tools from Mentor Graphics as its resolution enhancement solution for subwavelength semiconductor processes