Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "routability",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release PCB design software is even easier to use from
Zuken, which we summarised at the time by saying "Cadstar 9.0 features major usability and flexibility enhancements, along with functionality for adopting new technology".
A few weeks before,
we featured the news release Synopsys continues IC Compiler momentum from
Synopsys: "Synopsys has announced the 2006.06 release of IC Compiler, Synopsys' next-generation place-and-router".
In October 2005, we covered the news from Magma Design Automation
concerning its RTL-to-GDSII design flow
- take a look at Integrated flow cuts down image processor design
which says: "NuCore Technology, maker of the award-winning CleanCapture image processors, has standardised on Magma's RTL-to-GDSII design flow, including Blast Create and Blast Fusion".
Take a look also at the news release from Impulse Accelerated Technologies, Cutting a fast path to semiconductors,
as well as Faster timing closure with design environment from Actel Europe,
and Software supports structured ASIC design from eASIC Corp.
See also:
Two more patents for Monterey
(July 2003)
Monterey Design Systems has been issued two new patents by the United States Patent and Trademark Office, bringing the company's patent total to 14
Floorplanner helps FPGA designers to plan ahead
(July 2003)
The PlanAhead hierarchical floorplanner is the heart of the new silicon virtual prototyping solution from Hier Design for high-end field programmable gate arrays (FPGAs)
Backplane technology for multigigabit transmission
(February 2003)
Copper backplane and connector technology is growing to meet multigigabit transmission needs, says Gautam Patel, Signal Integrity Engineer at Teradyne
Programmable single-chip master/target PCI bridge
(November 2002)
The QL5632 is the latest addition to the QuickPCI family of secure, programmable master/target PCI bridge solutions
Chameleon changes to Monterey
(November 2002)
Chameleon Systems has purchased the entire Monterey Design Systems product line for use on its multi-million-gate streaming data processor
Logic libraries cut silicon costs
(October 2002)
Long known in the embedded memory market, Virage Logic is extending its role to the broader category of semiconductor IP platforms with its first foray into logic components
Capacity and accuracy boost RTL-to-GDSII solution
(October 2002)
Dolphin RTL is a second-generation RTL-to-GDSII solution, and the culmination of an 18-month collaborative effort between Monterey and Synplicity
Two more patents for Monterey
(July 2002)
Monterey Design Systems has been issued two patents by the US Patent and Trademark Office for its physical design technology, bringing its patent count to seven
Compiler reduces floorplanning iterations
(June 2002)
Floorplan Compiler is a high-end hierarchical design planner that enables designers to save time and money by creating high-quality floorplans in dramatically fewer iterations
RTL performance prototyping characterises soft IP
(May 2002)
Synopsys has introduced an RTL performance prototyping (RPP) flow using Physical Compiler for IP providers and IP integrators
Hands-on tutorial covers IP reuse at DATE
(February 2002)
Monterey Design Systems will present an in-depth, hands-on tutorial covering the challenges of integration and reuse of semiconductor IP at the DATE show next week in Paris
Monterey is a good fit for Flextronics
(January 2002)
Monterey Design Systems has signed a multi-year, multi-million-dollar agreement to provide Flextronics Semiconductor with access to its hierarchical System-Driven Physical Design methodology
Flextronics to deploy Monterey SDPD worldwide
(December 2001)
Monterey Design Systems has signed a multi-year multi-million-dollar agreement to provide Flextronics Semiconductor with its hierarchical System-Driven Physical Design (SDPD) methodology
Early assessment for Mitsubishi ASICs
(November 2001)
First Encounter software from Silicon Perspective Corp (SPC) has been integrated into the standard ASIC design flow of the Electronic Device Group of Mitsubishi Electric and Electronics USA
Physical design technology is now patented
(October 2001)
Monterey Design Systems has been issued patents numbered US 6,192,508 B1 and US 6,286,128 B1 by the United States Patent and Trademark Office
Physical design planner aids telecomms ASIC design
(October 2001)
NEC Electronics (Europe) has successfully used Synopsys' Chip Architect physical design planner to tape out a 3.8 million gate, 622MHz telecommunications ASIC chip
NEC tapes out ASICs with Plato's NanoRoute
(October 2001)
NEC Electronics has adopted NanoRoute from Plato Design Systems to tape out a number of its advanced ASICs
Advanced routing added to PCB design tools
(August 2001)
Mentor Graphics has announced the latest product release of its Expedition Series of PCB design tools, WG2000.5