Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "RTL compiler",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Reference methodologies speed ARM design from
Cadence Design Systems, which we summarised at the time by saying "Methodologies for two ARM processors provide enhanced design solutions to mutual customers designing multicore, low-power devices".
A few weeks before,
we featured the news release Multicore design optimises ARM performance from
Cadence Design Systems: "Design success prompts NEC to standardise on the Encounter platform as its tapeout methodology of choice for ARM processor implementations".
In July 2007, we covered the news from Cadence Design Systems
concerning its Logic Design Team Solution
- take a look at Logic designers get physical with floorplan data
which says: "'Design with physical' approach automatically delivers an accurate physical description of the design into the logic design stage".
Take a look also at the news release from Cadence Design Systems, Timing system is integral part of tapeout success,
as well as 65nm reference flow targets Common Platform from Cadence Design Systems,
and Compiler improves timing on large ASIC blocks from Cadence Design Systems.
See also:
IBM signs up for 65nm ASIC support
(November 2006)
Cadence Design Systems has signed an agreement to incorporate Encounter RTL Compiler global synthesis and Encounter Test technologies into the IBM 65nm ASIC design kit
Design and system interconnect go with the flow
(July 2006)
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0
News on the Encounter RTL Compiler from Denali Software
(June 2006)
Cadence Design Systems has announced support for Cadence Encounter RTL Compiler global synthesis on Databahn memory controller products
Timing-aware test generation cuts design delays
(June 2006)
Comit Systems has standardised its automatic test pattern generation (ATPG) flow on Cadence Encounter Test
News on the Encounter RTL Compiler from Cadence Design Systems
(March 2006)
Hitachi Communication Technologies has improved synthesis turnaround time by 50 to 70% with Cadence Encounter RTL Compiler global synthesis
Reference flow optimises 90nm SoC designs
(February 2006)
A 90nm reference flow addresses power-management and design-yield issues
Power-management methodology is enhanced
(February 2006)
The Silicon Design Chain Initiative has published announced a second, enhanced version of its power-management methodology
65nm design flow maximises platform benefits
(January 2006)
Fujitsu has adopted the Cadence Encounter digital IC design platform in its new internal reference design flow targeted at 65nm chips
News on the Encounter RTL Compiler GXL from Cadence Design Systems
(December 2005)
Encounter RTL Compiler GXL is an upgraded version of the Cadence Encounter RTL Compiler global synthesis technology, and the top-tier of the segmented Cadence synthesis product line
Platform enables early array signoff
(October 2005)
Toshiba Corporation and Toshiba Microelectronics Corporation have successfully taped out the first UniversalArray chip with Cadence Encounter digital IC implementation
Design flow supports latest ARM processor
(October 2005)
Cadence Design Systems has developed a high-performance design flow for the new ARM Cortex-A8 processor
News on the Encounter RTL Compiler from Cadence Design Systems
(October 2005)
Comit Systems has expanded its access to Cadence technology, and has standardised on Encounter RTL Compiler global synthesis, part of the Encounter digital IC design platform
Help at hand for PowerPC-based SoC design
(September 2005)
New services will aid SoC designers embedding PowerPC cores, including silicon validation of a new custom-synthesised design approach
ARM kits shorten time to productivity
(September 2005)
Cadence Design Systems and ARM have extended their design chain alliance to deliver further benefits to their mutual customers
News on the Encounter RTL Compiler from Cadence Design Systems
(August 2005)
Global UniChip Corporation of Taiwan has adopted Cadence Encounter RTL Compiler global synthesis to improve the quality of silicon of its hardened IP
News on the Encounter RTL Compiler from Cadence Design Systems
(August 2005)
Sunplus Technology Company of Taiwan has achieved an important production tapeout of a reduced-die-size consumer-electronics chip using Cadence technology
Low-power design successfully validated
(July 2005)
Accent has successfully validated a low-power design flow using the Cadence Encounter digital IC design platform and ARM Artisan physical IP
News on the Encounter RTL Compiler from Cadence Design Systems
(July 2005)
Canon has adopted Encounter RTL Compiler for its ASIC designs, further increasing momentum of RTL Compiler synthesis in Japan
RTL compiler speeds LCD controller to tapeout
(July 2005)
Seiko Epson Corp of Japan has doubled productivity in the production tapeout of a high-volume LCD controller chip using Cadence Encounter RTL Compiler synthesis
News on the Encounter RTL Compiler from Cadence Design Systems
(June 2005)
Nethra Imaging has successfully taped out its first product, the NI-2050 image processor designed for mobile handset applications, using Cadence Encounter RTL Compiler synthesis
News on the Encounter RTL Compiler from Cadence Design Systems
(June 2005)
Essence Technology of Taiwan has achieved an important sample tapeout with Cadence Encounter RTL Compiler synthesis, part of the Encounter digital IC design platform
IC design platform runs on 64bit Linux systems
(June 2005)
The popular Cadence Encounter digital IC design platform now runs on 64bit Intel Xeon processor-based systems with Linux to deliver higher performance and increased capacity for large designs
TSMC integrates nanometre design platforms
(June 2005)
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's latest reference flow
Reference flow set to boost 90nm SoC productivity
(May 2005)
Cadence Design Systems has outlined the next steps of its ongoing collaboration with IBM and Chartered Semiconductor Manufacturing to provide advanced solutions to enable SoC designs at 90nm
RTL compiler delivers production-cost savings
(May 2005)
Ricoh Company has successfully taped out a 3-million-gate chip ahead of schedule and with reduced gate count using the Cadence Encounter digital IC design platform, including RTL Compiler synthesis
Compiler helps Sanyo reduce power consumption
(January 2005)
Sanyo has achieved an important production tapeout with the Cadence Encounter digital IC design platform, including RTL Compiler synthesis
News on the Encounter RTL Compiler from Cadence Design Systems
(December 2004)
Oki has successfully taped out a chip for its uPlat SoC design platform with the new low-power capability of Cadence Encounter RTL Compiler synthesis
News on the Encounter RTL Compiler from Cadence Design Systems
(December 2004)
Toshiba America Electronic Components has introduced a design kit to support its custom SoC and ASIC customers using Cadence Encounter RTL Compiler synthesis
Fabless design house speeds to nanometre IC
(December 2004)
Fabless design house Azul Systems has successfully implemented a high-density, high-speed design using the Cadence Encounter digital IC platform and RTL compiler
Digital day for a workshop
(October 2004)
Cadence Design Systems is to stage an SoC workshop - digital day - on 2nd November 2004
RTL compiler is a qualified SoC success
(October 2004)
PalmChip Corp has qualified the Cadence Encounter RTL Compiler for implementation of its popular AcurX SoC platform
Reference flow supports 90nm process
(May 2004)
Cadence Design Systems has developed a qualified design reference flow validated as compatible with the IBM-Chartered 90-nanometre process platform
Compiler qualified for reference flow
(April 2004)
Taiwan Semiconductor Manufacturing Company is to integrate the Cadence Encounter RTL Compiler into its next-generation reference flow
Reference methodology supports speedy new cores
(April 2004)
Cadence Design Systems and MIPS Technologies have developed an optimised MIPS-Cadence Encounter Reference Methodology for customers of MIPS32 24K cores