Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "RTL Design",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Package deal cuts FPGA costs from
Xilinx, which we summarised at the time by saying "System Generator allows designers to graphically capture and verify high-performance DSP subsystems in Simulink using a Xilinx-optimised DSP blockset".
Earlier in the week,
we featured the news release Reference flow incorporates power reduction system from
Cadence Design Systems: "The Pride V1.5 flow incorporates the CPF-based Cadence low-power design solution to provide an automated and holistic low-power design flow from RTL design through GDS II tape-out".
In January 2008, we covered the news from Tensilica
concerning its UpZide reference design
- take a look at Reference deal facilitates high-speed internet
which says: "UpZide's solution builds on the existing and continued roll out of FTTN (fibre-to-the-network) VDSL2 deployment by significantly increasing both data rates and reach over the existing copper network".
Take a look also at the news release from Real Intent, Software rises to formal verification challenges,
as well as DSP tools receive speed boost from Xilinx,
and Functional verification expands in scope from Mentor Graphics UK.
See also:
On-the-fly error correcting code
(December 2006)
Tensilica has introduced its seventh-generation of Xtensa configurable processors, the Xtensa LX2 and Xtensa 7 cores
Cell-based ASICs drop in for FPGA replacement
(November 2006)
AMI Semiconductor can now convert 1.2V, 90nm FPGAs to 130nm cell-based ASICs
Software spots critical SoC issues early
(November 2006)
Cray has adopted the SpyGlass platform for its next generation ASIC projects
Emulator accelerates router ASIC proving
(October 2006)
Redback Networks has selected the Cadence Incisive Design Team Xtreme III acceleration and emulation solution
Core accelerates 8bit MCU applications
(October 2006)
Core processes one instruction cycle in a single clock cycle, enabling faster processing at lower frequencies, reduced noise and lower power consumption
SoC design services aid core deployments
(September 2006)
eInfochips now offers SoC design services for customers using Tensilica's Xtensa configurable processors or Diamond Standard processor cores
System shows timing, signal integrity and power
(September 2006)
Cadence Design Systems has further extended the capabilities of the Cadence Encounter digital IC design platform with the announcement of its Encounter Timing System
Synthesis tool cuts C-based design effort in half
(August 2006)
Fujitsu Microelectronics Solutions uses the Catapult Synthesis tool for use in wireless signal processing applications
Automated Design and Implementation Flow
(July 2006)
Cadence Design Systems and ARM have announced the joint development of the first automated RTL design and implementation flow for the ARM Cortex-A8 processor
RTL debugger makes sense of third-party IP
(July 2006)
A customisable tool helps designers of IP-based SoCs reduce the complexity of the debug process and makes it easier to understand and change register-transfer level code
Development environment adds more tools
(May 2006)
Actel has obtained the right to distribute the Synplify Pro, Identify and Synplify DSP software solutions to its customers as part of its Libero integrated design environment
Standard cell ASICs set to exploit market void
(April 2006)
A flexible 130nm standard cell technology offers a low-cost high-performance ASIC solution for broad-based applications
SystemVerilog support covers full design chain
(March 2006)
Synopsys now supports the SystemVerilog language throughout its suite of design and verification products, extending its SystemVerilog leadership and establishing another industry-first achievement
Functional verification takes tailored approach
(October 2005)
Cadence Design Systems has repackaged its Incisive functional verification platform, including full solutions with tailored and integrated products coupled with methodologies for unique segment needs
Teams turn to SystemVerilog-based verification
(October 2005)
The Incisive Design Team family is tailored for RTL design teams looking for a low-risk, yet powerful way to adopt SystemVerilog-based verification from plan to closure
ESL by any other name
(October 2005)
The latest hot topic in the chip design world recently has been electronic system level design, says Rob Irwin, Product Marketing Manager at Altium
Synthesis software boasts high quality of results
(September 2005)
Forte Design Systems has upgraded its industry-leading Cynthesizer behavioural synthesis solution to provide a more extensive production ESL design flow
Configurable processor flies on ST 90nm process
(August 2005)
STMicroelectronics has achieved first silicon success on a chip that proves Tensilica's Xtensa V configurable processor achieves a clock rate of 500MHz in a 90nm process technology
EDA tools get to grips with power managed designs
(August 2005)
MVSIM is billed as the world's first electronic design automation solution for verification of power managed designs
Platform accelerates structured ASIC to silicon
(August 2005)
This month, Fujitsu Microelectronics America will ship initial production volumes of a new, highly complex, structured ASIC using Cadence Encounter digital IC implementation
Sci-worx puts configurable processors to work
(April 2005)
Sci-worx is to design a range of SoC intellectual property blocks, including H.264, WMV-9 and MPEG-2 for high-definition TV, using multiple Tensilica Xtensa LX configurable processors
Cutting a fast path to semiconductors
(April 2005)
With special synthesis and processing, algorithms turn into silicon - but keep an eye on hardware
Configurable processors enable latest DSL design
(April 2005)
UpZide is to develop a reference design using multiple Xtensa LX processors from Tensilica to implement the VDSL2 standard
Calypto readies its design portfolio
(January 2005)
Calypto Design Systems has unveiled its strategy for bridging the gap between electronic system level design and integrated circuit implementation
News on the C to RTL design tools from Impulse Accelerated Technologies
(September 2004)
The newest edition of Impulse's CoDeveloper C to RTL design tools allows FPGA users to compile C to Altera's highest-performance programmable platforms
News on the C to RTL design tools from Impulse Accelerated Technologies
(September 2004)
CoDeveloper makes it possible to describe, debug and test mixed hardware/software applications using standard C development tools such as Visual Studio and GCC/GDB
Hardware design in an SoC world
(July 2004)
Adopting a virtual-prototype-based SoC development process offers all-round benefits, and makes the hardware designer's job easier, argues Graham Hellestrand, founder of Vast Systems Technology
Automated functional analysis speeds verification
(June 2004)
Periscope is an automated functional analysis solution claimed to significantly reduce time and effort spent in the verification process for complex systems on chip (SoCs)
SystemC models run faster than RTL
(June 2004)
The Univers Modeler is an extension to Adveda's ultra-fast RTL simulator, which generates a SystemC wrapper or a PLI/FMI wrapper around a native simulation model, compiled within this simulator
Speedy route from SystemC to RTL
(May 2004)
Cynthesizer is billed as the first behavioural synthesis product to offer an implementation path from SystemC to RTL, verification and cosimulation
Learn all about SystemVerilog for free
(January 2004)
Four leaders in advanced design and verification technologies are sponsoring free SystemVerilog technical seminars and product demonstrations in Israel, Germany, the UK and Japan
Smith takes charge
(August 2003)
Well known EDA executive Robert (Bob) P Smith, has been appointed to the position of President and Chief Executive Officer (CEO) at InTime Software
Early analysis aids power-aware design
(July 2003)
Tensilica is using PowerTheater to analyse power early and and often at the RTL stage
Enhanced RTL debug software supports more devices
(June 2003)
Identify is the industry's only software tool that allows FPGA prototyping designers to functionally debug their hardware directly in their RTL source code