Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "RTL Source",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release MRAM emulator aids ASIC prototyping from
Silicon Laude, which we summarised at the time by saying "Multipurpose in-circuit emulator can emulate radiation hardened synchronous MRAM and ASICs containing up to one million gates".
The same day,
we featured the news release ASIC verification nears full device speed from
Synplicity: "Software offers full visibility into FPGA-based ASIC and ASSP prototypes enabling designers to find, fix and verify functional errors at speeds approaching that of the final device".
In April 2007, we covered the news from Synopsys
concerning its 2007.04a DesignWare IP for AMBA 2 and AMBA 3 AXI
- take a look at DesignWare IP for AMBA 2 and AMBA 3 AXI protocols
which says: "Latest release of DesignWare IP for the ARM AMBA 2 and AMBA 3 AXI protocols allows designers to integrate the high-speed protocol easily into their chips and focus on value-added differentiation".
Take a look also at the news release from eASIC Corp, Amba Platform IP runs on structured ASICs,
as well as IP puts PCI Express on Amba-based SoCs from Synopsys,
and MCU development runs from FPGA to ASIC from Domain Technologies.
See also:
Development environment adds more tools
(May 2006)
Actel has obtained the right to distribute the Synplify Pro, Identify and Synplify DSP software solutions to its customers as part of its Libero integrated design environment
Platforms support multithreaded SPARC designs
(March 2006)
Synopsys is providing Galaxy Design and Discovery Verification Platform support for Sun Microsystems' UltraSPARC T1 processor
IBM recognises pioneering work in SoC project
(March 2006)
A project successfully completed for Broad Reach Engineering has led to Synopsys winning IBM's prestigious Beacon Award for the best IBM Power Architecture solution
Decoder has main multimedia standards covered
(October 2005)
Hantro's 7170 decoder is billed as the first hardware solution to combine all of the key formats for enabling mobile multimedia in one design
Prototyping family extends to single-chip designs
(April 2005)
Synplify Proto is the first prototyping tool to address the need for single FPGA prototyping by integrating logic synthesis with debugging capabilities
FPGA synthesis software comes up to date
(September 2004)
Synplicity has released new versions of its FPGA synthesis and physical synthesis software solutions
Family group to unify verification
(February 2004)
The Univers product family is a unified verification solution for both hardware and embedded software design of SoCs
Software speeds RTL debugging
(December 2003)
Synplicity has enhanced its Identify RTL debugging software to further accelerate FPGA hardware debugging
Modem IP core meets 802.11g
(December 2003)
NewLogic Technologies has developed an IEEE802.11g standard compliant DSSS/OFDM modem in RTL source code as part of its of its Wild family
IP embeds High-Speed USB host controllers
(October 2003)
ARC International has a new family of single- and multiport USB High-Speed (USB-HS) host controllers
Enhanced RTL debug software supports more devices
(June 2003)
Identify is the industry's only software tool that allows FPGA prototyping designers to functionally debug their hardware directly in their RTL source code
Desktop system rips through timing closure
(June 2003)
Time Director is the first-ever product for the electronic design desktop to enable cost-effective rapid timing closure with performance that accelerates existing methods by a factor of 40-50x
Cores turn FPGAs to PowerPC interfacing
(May 2003)
Eureka Technology has optimised three PowerPC interface IP cores for use with Actel's nonvolatile ProASIC Plus, Axcelerator, SX-A and RTSX-S FPGAs
ARCtangent-A5 AMBA bus support on the way
(October 2002)
ARC International has announced the ARCtangent-A5; AMBA bus support will arrive later in 2002 and it already supports the emerging, open-standard BVCI protocol
Core cuts cost and complexity of Bluetooth SoCs
(September 2002)
The DesignWare BlueIQ core is a complete solution enabling designers to quickly add Bluetooth capability to SoC designs
Codec provides improved image compression
(May 2002)
inSilicon Corp has added the JPEG2000 codec to its existing portfolio of image compression semiconductor intellectual property
IP puts Gigabit Ethernet MAC on chip
(April 2002)
The latest addition to the Gigabit Ethernet intellectual property product line from inSilicon Corp is a Gigabit Ethernet MAC subsystem (GMAC subsystem)
Analysis tool checks testability of RTL code
(January 2002)
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level
IP puts SoCs on the PCIbus
(December 2001)
Eureka Technology is to make available the plug-in IP modules it developed for the ARCtangent processor to connect to memory devices and the PCIbus
Cores for high-speed network infrastructure
(October 2001)
Cypress Semiconductor and MorethanIP are to make MorethanIP's IP cores available for the Cypress PSI family of programmable physical layer devices and the Delta39 family of CPLDs
Bluetooth baseband processor available on FPGA
(June 2001)
NewLogic today announced the immediate availability of its Boost Lite Bluetooth baseband processor core for use in Xilinx Virtex-II and Virtex-E FPGAs
MP3 player comes in RISC-based SoC
(March 2001)
Palmchip has announced an MP3 SoC hardware platform featuring a configurable 32bit RISC/DSP processor licensed from ARC Cores