Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "RTL Synthesis",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Environment to make more of multigigahertz FPGAs from
Achronix Semiconductor Corporation, which we summarised at the time by saying "Achronix Semiconductor and Mentor Graphics collaborate to provide a comprehensive FPGA design environment for Achronix' high performance FPGAs".
A couple of weeks before,
we featured the news release Programmable logic design suite is free to use from
Lattice Semiconductor UK: "ispLever Classic is a comprehensive software design tool suite that supports all mature Lattice programmable devices".
In April 2007, we covered the news from Synopsys
concerning its Design Compiler 2007
- take a look at Design synthesis takes topographical route
which says: "Topographical technology allows designers to accurately estimate a chip's power consumption during synthesis and address any power issues early in the design cycle".
Take a look also at the news release from Actel Europe, Design environment supports low-power FPGAs,
as well as Topographical technology in new 65nm methodology from Synopsys,
and 5uA standby power consumption from Atmel Corporation.
See also:
Topographical technology shortens time to market
(August 2006)
Progate Group Corporation has adopted Synopsys' Design Compiler topographical technology to help accelerate time to market for its products
Library reduces delay in IC designs
(July 2006)
Synopsys expands DesignWare Library with more than 20 new IP components
Processor configuration tool Encounters support
(June 2006)
Using ARChitect, ARC licensees now can produce RTL, synthesis and floorplanning scripts that are tuned to the Encounter reference methodology
System level tool supports complex designs
(June 2006)
Catapult SL is billed as the first high-level synthesis tool to automatically create high-performance multiple-block subsystems from pure sequential ANSI C++
Pioneer adopts synthesis tools
(May 2006)
Pioneer Corporation's Mobile Systems Development centre has chosen Catapult C Synthesis and Precision RTL synthesis tool to create digital signal processing (DSP) hardware
Chinese designers adopt Galaxy
(April 2006)
Hisilicon Technologies has adopted Synopsys' Galaxy Design Platform as its primary IC design flow for 130nm designs
SystemVerilog pioneers recognised by IEEE
(January 2006)
Dennis Brophy and Dave Rich have received the IEEE Working Group Chairman's Award for their contributions to the IEEE1800-2005 'SystemVerilog' standard
Design platform keeps 65nm processor on schedule
(December 2005)
The Cadence Encounter digital IC design platform has helped PA Semi develop its new 65nm multicore PWRficient processor with a successful test-chip tapeout in March 2005
Adaptive scan technology reduces tester costs
(November 2005)
Genesis Microchip, supplier of display image ICs, has successfully deployed DFT MAX adaptive scan technology to reduce tester costs
Marvell goes from RTL to GDSII
(October 2005)
Marvell has adopted Synopsys' Galaxy Design Platform as a RTL-to-GDSII design solution to develop networking and storage products
PLDs cross over into FPGA applications
(July 2005)
Lattice Semiconductor has launched its new MachXO family with the immediate availability of its first two members, the MachXO256 and MachXO640
Novel route to personalised processing
(June 2005)
Corxpert technology automates the path for software developers to develop custom instructions to improve processor performance, creating differentiated products
Panasonic signs up for high-level synthesis tools
(June 2005)
Panasonic Communications has selected the Mentor Graphics Catapult C Synthesis tool after evaluating leading high-level synthesis tools
Sanyo opts for algorithmic synthesis
(May 2005)
Sanyo Electric Co has selected the Mentor Graphics Catapult C Synthesis tool after an evaluation comparing leading high-level synthesis tools
Programmable logic design tools upgraded
(May 2005)
The latest version of the ispLever programmable logic design tool suite incorporates major additions and improvements to design flow and documentation
Fraunhofer Institute adopts C synthesis tool
(March 2005)
The Fraunhofer Institute for Integrated Circuits IIS has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast applications
RTL synthesis upgrades FPGA design software
(January 2005)
Lattice Semiconductor has announced the immediate availability of the Mentor Graphics' Precision RTL synthesis tool for customer use
News on the Precision RTL Synthesis and Leonardo Spectrum from Mentor Graphics UK
(January 2005)
Mentor Graphics' suite of advanced synthesis products supports Altera's newly introduced HardCopy II structured ASIC family
News on the Precision RTL Synthesis from Mentor Graphics UK
(January 2005)
Mentor's suite of advanced synthesis products has gained added support for Actel Corp's newly introduced ProASIC3 and ProASIC3E field programmable gate arrays (FPGAs)
ESL design environment covers more devices
(December 2004)
Version 3.1 of the DK Design Suite provides high-level system codesign, verification and C-based synthesis for complex algorithm implementation to high-density FPGA and programmable SoC devices
Tool suite boasts faster FPGA design
(November 2004)
The latest release of the ispLever programmable logic design tool suite offers a comprehensive upgrade and enhancement in performance and functionality
Faster timing closure with design environment
(November 2004)
Actel's Libero Integrated Design Environment (IDE) offers strengthened support for the company's antifuse-based, single-chip Axcelerator field-programmable gate arrays (FPGAs)
Mentor deal extends tool offerings
(October 2004)
Lattice Semiconductor has signed a multi-year extension and expansion of its OEM agreement for Mentor Graphics' synthesis and simulation tools
Synthesis tools support Virtex-4 FPGAs
(September 2004)
The Mentor Graphics suite of advanced synthesis products will support the newly introduced Virtex-4 field-programmable gate arrays (FPGAs) from Xilinx
Software supports latest budget FPGA family
(July 2004)
Leading EDA vendors have rolled out support for the new Cyclone II FPGA family - billed as the industry's lowest ever cost FPGAs
Synthesis tool speeds C designs to RTL
(June 2004)
Catapult C is billed as the only algorithmic synthesis tool that uses pure, untimed C++ to create quality RTL descriptions up to 20 times faster than traditional manual methods
Timing estimation to become placement aware
(February 2004)
Synplicity is to offer timing estimation based on placement and automatic initial floorplanning as an alternative to traditional wireload model-based RTL synthesis in future releases of Synplify ASIC
IEEE endorses Accellera standards
(October 2003)
Accellera's Advanced Library Format (ALF) has been approved as IEEE1603-2003
FPGA software moves to a new level
(July 2003)
The latest version of FPGA Advantage features a new design cockpit that integrates recent updates to the HDL Designer Series, ModelSim and Precision RTL Synthesis products
FPGA design flow runs from IP to the PCB
(May 2003)
Mentor Graphics has developed a comprehensive FPGA design flow that expands traditional FPGA tools with new technologies to address emerging challenges of complex FPGA designs
RTL compiler synthesis speeds multicore design
(May 2003)
Toshiba America Electronic Components has used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a 530MHz synthesisable 64bit dual-issue MIPS core
Integrated design and verification for Spartan-3
(April 2003)
Mentor Graphics is providing comprehensive design tool support for the new Spartan-3 platform FPGAs from Xilinx
Tools provide new dimensions in design capture
(November 2002)
nVisage is a novel 'multidimensional' design capture tool that allows design engineers to capture the conceptual design of their entire electronic system into a single, integrated environment
Logic BIST reduces SoC test data and time
(October 2002)
Synopsys has entered the logic BIST market with DFT Compiler SoCBIST, offering deterministic logic BIST capabilities