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‘Testbenches’
A Electronicstalk guide
Start with the news release
IP package creates full Serial ATA interface from
Synopsys, which we summarised at the time by saying "Comprehensive high quality IP solution helps designers reduce the risk and cost of integrating the Serial ATA interface into their SoC designs.".
Several months prior to that,
we featured the news release Verification IP products suit OVM users from
Cadence Design Systems: "The AMBA 3 AXI and AMBA AHB VIP are now available as multilanguage universal verification components (UVC) and are the first to provide OVM support within the Cadence VIP portfolio. ".
In June 2008, we covered the news from Synopsys
- take a look at Manual formalises low-power verification
which says: "The "Verification methodology manual for low power designs" will enable rapid and broad deployment of industry best practices for comprehensive verification of low power designs.".
Take a look also at the news release from OneSpin Solutions, Verification promises gap-free performance,
as well as Verification methodology goes online from Synopsys,
and Verification startup aims to reassure IC designers from Nusym Technology.
Latest stories...
VMM methodology speeds I/O design (May 2008)
Pairing the VMM methodology with the VCS tool enabled NextIO to efficiently build highly accurate system-level and unit-level simulation environments that quickly identify design bugs.
Systematic verification boosts productivity (February 2008)
Process systematically delivers predictable, repeatable verification results for complex modules and IP, accelerating the gap-free formal verification that ensures first-time error-free operation.
Software rises to formal verification challenges (December 2007)
Ascent finds bugs in RTL designs and improves design quality, with significantly higher performance compared with Real Intent's previous generation of automatic verification software.
Verification line handles complex chip designs (December 2007)
New offerings in the Incisive Enterprise verification family enable users to handle designs containing hundreds of millions of logic gates.
Acquisition addresses power management challenges (June 2007)
ArchPro's silicon-proven power management technologies are a natural fit with Synopsys' advanced verification platform.
Graphical approach eases complex verification (May 2007)
Graph based functional test synthesis tool helps users to understand, define and analyse complicated verification requirements.
Board sets the standard in verification (May 2007)
The Accellera Board of Directors has approved the SCE-MI 2.0 specification as an Accellera verification standard.
Triple approach verifies clock domain crossing (April 2007)
All-new new approach to CDC verification is engineered to verify that data traversing asynchronous clock domains on ASIC, SoC or FPGA devices is received reliably.
Further reading
-
Writing testbenches using SystemVerilog
A new book aims to help design engineers learn advanced verification techniques using the SystemVerilog IEEE1800-2005 standard language.
