Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Vera",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Verification IP automates manual register checks from
Denali Software, which we summarised at the time by saying "IP automates functional verification of configuration registers for system-on-chip designs".
Several months prior to that,
we featured the news release Verification automation enters third generation from
Jeda Technologies: "NSCa is a comprehensive native SystemC assertion development and debug environment for both the transaction-level and cycle-level design phases".
In February 2006, we covered the news from Synopsys
concerning its Pioneer-NTB
- take a look at IEC award for testbench automation tool
which says: "The Pioneer-NTB SystemVerilog testbench automation tool has been honoured as the recipient in the design verification category in the annual IEC DesignVision Awards".
Take a look also at the news release from Synopsys, Verification platform proves complex switch chips,
as well as Marvell goes from RTL to GDSII from Synopsys,
and Simulator made for networked design verification from Aldec.
See also:
ASIC designer accelerates chip development
(July 2005)
Silicon Logic Engineering is using the VCS comprehensive RTL verification solution and Vera testbench automation tool to accelerate its chip development process
Collaboration aims for systems-level SoC design
(June 2004)
Synopsys and Virtio are collaborating on a comprehensive electronic system level (ESL) solution that connects hardware and software development flows for leading SoC platforms
Synopsys extends library support
(June 2004)
Synopsys and ARM are collaborating to deliver Amba AXI verification intellectual property through Synopsys' DesignWare Library and DesignWare Verification Library
Testbench technology aids RTL verification
(May 2004)
The latest release of the VCS RTL verification solution extends its built-in testbench capabilities to include a rich set of advanced technologies
News on the Vera 6.2 from Synopsys
(January 2004)
The latest release of the Vera advanced testbench automation tool is an integral part of the Synopsys Discovery verification platform
Tools to run faster on 64bit platforms
(November 2003)
Synopsys is porting its Galaxy design and Discovery verification platforms to run on AMD64 architecture-based processors running the Red Hat Enterprise Linux, Version 3 operating system
Tools run faster on latest 64bit systems
(October 2003)
The key components of Synopsys' Galaxy design and Discovery verification platforms are now available on Intel Itanium 2-based systems running the 64bit Linux operating system
Verification focuses on telecomms SoCs
(December 2002)
Telecom Workbench is a new product that addresses functional and conformance verification of multistandard SoCs
Design methodologies speed time to ARC silicon
(September 2002)
Synopsys Professional Services has assisted ARC International with two strategic projects that enable ARC and its customers to integrate ARCtangent microprocessor cores more quickly and reliably
Vera speeds verification of Sonet/SDH chip
(September 2002)
NEC Electron Devices has successfully verified its latest Sonet/SDH framer physical layer chip with Synopsys' Vera testbench automation tool
Synopsys tools join the ARC design flow
(June 2002)
ARC International has made two important new technology developments in integrating Synopsys' tools into its design flow
Synopsys puts its weight behind Accellera
(June 2002)
Synopsys has affirmed its support for SystemVerilog 3.0 and has donated several technologies to Accellera for SystemVerilog version 3.1
Simulator spans from concept to implementation
(February 2002)
Synopsys has added a commercial SystemC simulator to its latest CoCentric System Studio release
News on the Vera 5.0 from Synopsys
(November 2001)
Synopsys has integrated its Vera and VCS tools to boost verification performance
Programme aids IP and verification for OpenVera
(October 2001)
Synopsys has launched the OpenVera Catalyst Programme, with 20 design and verification service companies participating
Verilog simulator gains verification capabilities
(September 2001)
VCS 6.0.1 is the latest release of the industry's highest performance Verilog simulator from Synopsis
The art of verification with VERA
(September 2001)
Verification Central and Synopsys have jointly launched a new book: 'The art of verification with VERA', by Faisal Haque, Khizar Khan and Jonathan Michelson
TI adopts Scirocco for its RTL regression farm
(June 2001)
Texas Instruments has selected Synopsys' Scirocco VHDL simulator as a key component of the verification suite for its high-performance DSP designs