Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Verilog",
and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
Let me be your guide.
Start with
the news release Kit eases convertor selection and development from
Analog Devices, which we summarised at the time by saying "The CED toolkit platform is claimed to be capable of shaving six to eight weeks off the convertor selection and design-in process".
A couple of weeks before,
we featured the news release Language link eases verification from
OneSpin Solutions: "OneSpin's 360 MV ensures that all functional errors in complex digital modules and intellectual property (IP) are detected".
In December 2007, we covered the news from SystemCrafter
concerning its SystemCrafter SC
- take a look at Automatic synthesis from SystemC to HDL
which says: "New version has improved SystemC coverage, and now allows synthesis to Verilog as well as VHDL".
Take a look also at the news release from DxO Labs, Silicon IP upgrades handset image processing,
as well as FPGA synthesis accepts VHDL and Verilog from Mentor Graphics UK,
and Software partnership aids FPGA simulation from Zuken.
See also:
Embedded computing language released
(October 2007)
Embedded Matlab users can avoid the time-consuming and error-prone process of rewriting Matlab algorithms in C
Programmable systems have power to spare
(August 2007)
Design combines Fusion Programmable System Chip with CoreABC microcontroller to provide a complete system management solution using a fraction of the Fusion part's logic tiles
FPGA software simplifies I/O assignment
(August 2007)
PinAhead technology provides the ability to assign interface I/O groups to I/O pins simply by dragging into a graphical representation of the FPGA
DC/DC convertor IP runs on standard CMOS process
(August 2007)
IP core allows SoC designers to integrate DC/DC convertor functionality into their designs and avoid the additional expense of higher voltage process options
Smart design software for faster FPGAs
(June 2007)
Integrated FPGA design environment gains new design entry capability that enables users to design at a higher level of abstraction, speeding time to market
Methodology combines design with verification
(May 2007)
Fujitsu Kyushu Network Technologies is using the Cadence Incisive plan-to-closure methodology for SystemVerilog verification in RTL logic design teams
Synthesisable building blocks jumpstart designs
(May 2007)
The latest version of Cynthesizer is billed as the first high-level synthesis product to offer a direct path from high-level SystemC to GDSII
MRAM emulator aids ASIC prototyping
(May 2007)
Multipurpose in-circuit emulator can emulate radiation hardened synchronous MRAM and ASICs containing up to one million gates
Model integration finds more bugs with MIPS
(May 2007)
Carbon Design Systems has integrated its models with the MIPSsim instruction set simulator and software debugger to provide complete validation for MIPS-based SoCs
Video encoder core on structured ASICs
(March 2007)
The H264-MCE multichannel baseline video encoder core from CAST is now available for implementation in Nextreme structured ASIC devices
Bluetooth IP embeds enhanced datarate
(March 2007)
IP platform for Bluetooth Specification Version 2.0 + EDR provides enhanced datarate performance to chip designers
SoC models are fit for system level design
(March 2007)
Models from SOC-VSP software plug-and-play with the Platform Architect design environment from CoWare
IP developer joins EEMBC's networking subcommittee
(March 2007)
Netcleus Systems Corporation has joined the Embedded Microprocessor Benchmark Consortium's (EEMBC's) networking subcommittee
Nominations for Techical Excellence award invited
(February 2007)
Accellera is inviting the the electronic design community to nominate an individual for its 4th annual Technical Excellence Award
FPGAs boost DSP bandwidth
(February 2007)
The SXT platform establishes an industry record for DSP performance delivering 352 GMACs at 550MHz, while consuming 35% less dynamic power compared with previous 90nm generation devices
Structured ASICs gain gigabit Ethernet option
(January 2007)
Dynamically configurable trimode Ethernet MAC core will enable engineers to build robust Ethernet line card, NIC card or switching applications operating at 10/100 or 1000Mbit/s
Virtual platforms aid exploration and development
(January 2007)
CoWare and Tenison Design Automation have jointly announced significant enhancements to the two companies' integrated design flow
Compiler technology complements HyperTransport
(January 2007)
CebaTech has joined the HyperTransport Technology Consortium
Aldec software is tailored to Lattice FPGA lines
(January 2007)
Lattice Semiconductor is to offer its customers a special edition of Aldec's Active-HDL Designer Edition tools for FPGA design
Compiler generates RTL from untimed ANSI C
(January 2007)
C-to-RTL compiler works efficiently on large, complex designs at a high level of abstraction and then automates the process of creating high-performance hardware solutions
Patent application for FPGA IP Core Middleware
(December 2006)
A breakthrough in Standards-based inter-operability and portability for embedded systems software - without sacrificing any of the performance advantages of FPGA acceleration
Four video processor engines introduced
(December 2006)
Tensilica has introduced four new Diamond Standard VDO (ViDeO) processor engines customised for multi-standard, multi-resolution video in System-on-Chip (SOC) designs
Prototyping platforms put FPGAs in avionics
(November 2006)
Actel has partnered with Aldec to offer two highly integrated solutions designed specifically for FPGAs in high-reliability avionics and aerospace applications
Verification environment moves up to Stratix III
(November 2006)
Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family
Synthesis software is optimised for Stratix III
(November 2006)
Synplicity has upgraded its industry-leading Synplify Pro FPGA synthesis and Synplify DSP true DSP Synthesis software to support Altera Corp's new low-power, high-performance Stratix III FPGAs
Simulator expands high-frequency capabilities
(November 2006)
Nexxim v3.5 is the latest version of Ansoft's high-performance circuit simulator
HDL simulator upgrades performance
(October 2006)
The latest Riviera-Pro release adds high performance SLP (system level platform) technology and is an important milestone for Aldec in Verilog RTL, gate and timing simulation
MCU development runs from FPGA to ASIC
(October 2006)
MCU netlist library and software development kit for use with Actel FPGAs includes a royalty-free licence to implement resulting microcontroller designs in a Tekmos merged ASIC
IP code embeds JTAG communication
(October 2006)
JTAG Technologies has released its TapCommunicator hardware product as IP code for embedding into ASICs and FPGAs
Coder provides link from system model to device
(September 2006)
The Simulink HDL Coder automatically generates synthesisable hardware description language code from models created in Simulink and Stateflow software
Verification IP covers OCP-based SoCs
(September 2006)
Verification IP for the OCP interface responds to customer demand for using the DesignWare Library and VCS Verification Library to verify systems and cores that use OCP
Mathworks introduces link for modelsim 2
(July 2006)
Tool upgrade adds direct verilog support; collaboration with Mentor Graphics, streamlines verification process and enhances model-based design
Help for system-on chip designers
(July 2006)
Concept Engineering introduces SGvision Pro to help system-on chip designers analyse and debug mixed-mode circuits
RISC processor cores come without royalties
(July 2006)
Mosis, the multiproject wafer (MPW) services provider, has partnered with Cambridge Consultants to offer customers royalty-free access to the XAP4 and XAP5 16bit RISC processor cores