Intellectual property cores
(a sub category of Design and development)
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I2S-SC controller introduces TDM mechanism
Evatronix has introduced the I2S-SC controller IP, which is compatible with the Philips I2S specification and all its modes.
News from Evatronix, Mar 16, 2010
Driver improves Nand Flash application development
Evatronix has introduced the latest release of the software driver for its Nand Flash memory controller IP core.
News from Evatronix, Mar 15, 2010
IP core implements wide set of peripherals
Evatronix has released the 80186EC IP core - a 16-bit microprocessor compatible with the 80c186ec chip from Intel and can address a variety of possible applications.
News from Evatronix, Mar 15, 2010
Nsys releases Functional Coverage Test Suites
Nsys Design Systems has announced the availability of Functional Coverage Test Suites for its Nsys Verification Suite (nVS) portfolio.
News from Nsys Design Systems, Mar 10, 2010
LSI adds processor core and memory blocks to range
LSI has announced the addition of the multicore-capable PowerPC 476 microprocessor core and high-speed, embedded DRAM memory blocks to its portfolio of custom silicon intellectual property (IP).
News from LSI Europe, Jan 21, 2010
Macraigor ports technology to Cortex-A8 processor
Macraigor Systems has ported its its On-Chip Debug Technology (OCDemon), GNU Tools Suite and Eclipse Ganymede/Galileo platform to the ARM Cortex-A8 processor.
News from Macraigor Systems, Dec 16, 2009
Tensilica provides design-flow support for DPUs
Tensilica provides out-of-the-box automated design-flow support for key technologies within Synopsys' Galaxy Implementation Platform.
News from Tensilica, Dec 10, 2009
Actel extends Core8051s support for FPGAs
Actel has extended Core8051s support for its line of high-reliability Axcelerator, radiation-tolerant RTAX and low-power Igloo FPGAs.
News from Actel Europe, Dec 3, 2009
Evatronix seminars discuss Superspeed technology
Evatronix has announced that it will will host a series of technical seminars on 2 December at the IP-ESC Conference in Grenoble, jointly with speakers from the industry.
News from Evatronix, Nov 27, 2009
Evatronix Nand Flash controller meets ONFi spec
Evatronix SA has updated its Nand Flash memory controller to meet the latest specifications of the Open Nand Flash interface (ONFi) and now supports the newest High Speed Nand Flash.
News from Evatronix, Nov 25, 2009
Lattice and Praesum release RapidIO 2.1 IP core
Lattice Semiconductor and Praesum Communications have announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA range.
News from Lattice Semiconductor UK, Nov 25, 2009
Synopsys releases data converter IP solutions
Synopsys has released a range of data converter IP solutions for 40nm process technologies.
News from Synopsys, Nov 25, 2009
Video encoder IP core has H.264 HP capability
Imagination Technologies has announced PowerVR VXE380, the latest member of its third-generation video encoder IP family.
News from Imagination Technologies, Nov 20, 2009
Serial IP core supports RapidIO 2.1 specification
Altera has announced the first intellectual property (IP) core supporting the RapidIO 2.1 specification.
News from Altera Europe, Nov 17, 2009
Digi launches core module for wireless multimedia
Digi International has introduced the Connectcore Wi-MX51, a core module designed for low-power, wireless-multimedia applications.
News from Digi International, Nov 9, 2009
Tensilica introduces Xtensa LX3 DPU core
Tensilica has introduced the Xtensa LX3 high-performance dataplane processor (DPU) core, optimised for digital signal processing (DSP) and control in the system-on-chip (SoC) dataplane.
News from Tensilica, Nov 3, 2009
Audio IP fits easily into embedded designs
Synopsys has brought out the Designware 96 dB Hi-Fi Audio IP in the SMIC 65nm process.
News from Future Waves, Oct 30, 2009
Cypress announces IP elements for PSoC 3
Cypress Semiconductor has announced the availability of over 30 intellectual property (IP) elements for its PSoC 3 programmable system-on-chip architectures.
News from Cypress Semiconductor, Oct 29, 2009
Tensilica announces customisable processor
Tensilica has introduced the Xtensa 8 customisable processor, the eighth generation of its low-power dataplane processor cores (DPUs).
News from Tensilica, Oct 21, 2009
Lora semiconductor IP allows long-range wireless
Cycleo, an IP and services provider, has announced Lora, a semiconductor IP based on a disruptive technology and allowing robust long-range wireless communications at low power.
News from Cycleo, Sep 18, 2009
ARM launches Cortex-A9 hard macros
ARM has announced the development of two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process.
News from ARM, Sep 17, 2009
TSMC adopts Synopsys's HSIM circuit simulator
Synopsys has announced that TSMC has adopted its HSIM hierarchical Fastspice circuit simulator for its sub-40nm memory intellectual-property (IP) characterisation flow.
News from Synopsys, Sep 16, 2009
Altera RapidIO passes Riolab testing
Altera Corporation has announced that its RapidIO Megacore function, version 9.0, successfully passed Riolab's Device Interoperability Level-3 (DIL-3) testing.
News from Altera Europe, Sep 3, 2009
Tensilica engine provides performance from C code
Tensilica has introduced the low-power ConnX D2 16-bit dual-MAC DSP engine for its Xtensa LX dataplane processor cores for SOC (System-on-Chip) designs.
News from Tensilica, Aug 27, 2009
Nsys supplies verification IP to Nethra Imaging
Nethra Imaging has selected Nsys systems for its verification IP needs in its video/broadcast, medical, storage, and test/measurement markets applications.
News from nSys Design Systems, Aug 27, 2009
Showing 1-25 of 1571 articles
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What is it?
Intellectual property cores:
A semiconductor intellectual property core, IP core is a reusable unit of logic, cell, or chip layout design that is the intellectual property of one party. IP cores are usually portable in the sense that they can be inserted in many designs. They come in three forms: hard, firm or soft cores, relating to their level of adaptability to various applications.
Featured articles
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I2S-SC controller introduces TDM mechanism
Evatronix has introduced the I2S-SC controller IP, which is compatible with the Philips I2S specification and all its modes.
-
Driver improves Nand Flash application development
Evatronix has introduced the latest release of the software driver for its Nand Flash memory controller IP core.
