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Design and Development Software
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Altium Designer wins IEC DesignVision Award
Altium's unified electronic product development solution, Altium Designer 6, has been awarded a prestigious International Engineering Consortium's (IEC) DesignVision Award at DesignCon 2007.
News from Altium ( 5 February 2007)
Verification and custom businesses lead growth
Cadence Design Systems has reported fourth quarter 2006 revenue of US $431 million, an increase of 14% over the $378 million reported for the same period in 2005.
News from Cadence Design Systems ( 5 February 2007)
Freescale takes kit route to analogue improvement
Freescale Semiconductor has adopted the Cadence AMS Methodology Kit to leverage key capabilities of advanced analogue/mixed-signal technologies, flows and methodologies.
News from Cadence Design Systems ( 2 February 2007)
Distributors take boundary scan to 21 countries
To meet the demand for its boundary scan test system, XJTAG has appointed eight new distributors.
News from XJTAG ( 2 February 2007)
Award for planning and analysis software
Xilinx PlanAhead 8.2 design planning and analysis software has received a 2007 DesignVision Award.
News from Xilinx ( 1 February 2007)
Sponsorship underlines open source commitment
TimeSys Corp is sponsoring The Open Source Summit, presented by The IndUS Entrepreneurs (TiE) Pittsburgh.
News from TimeSys Corp ( 1 February 2007)
Proposal enhances IEEE1481 SPEF standard
The IEEE1481 working group has approved Synopsys' proposal for an extension to the Standard Parasitic Exchange Format (SPEF) for process and temperature variation.
News from Synopsys ( 1 February 2007)
Power saving design cuts wireless silicon by 30%
User application article Jennic has successfully taped out an embedded ZigBee IC wireless microcontroller with the Cadence Low-Power Solution.
News from Cadence Design Systems ( 1 February 2007)
Zero-cost licensing for Ada
Aonix has announced a new "zero-cost" licence model for its ObjectAda for Linux product.
News from Aonix ( 1 February 2007)
Mobile audio chip cuts power and boots first time
User application article Silicon and Software Systems has achieved record-breaking production success using its low-power SoC design flow based on the Cadence Low-Power Solution.
News from Cadence Design Systems (31 January 2007)
Prototyping software makes the most of 65nm FPGAs
ASIC RTL prototyping software delivers optimal support for the Xilinx Virtex-5 family of 65nm FPGAs.
News from Synplicity (31 January 2007)
Software preserves low-power design intent
The Cadence Low-Power Solution is billed as the industry's first fully integrated flow for logic design, verification and implementation of low-power chips.
News from Cadence Design Systems (30 January 2007)
On-chip FPGA verification runs faster
Software for on-chip FPGA verification leverages the advanced 65nm ExpressFabric architecture of the Virtex-5 platform family.
News from Xilinx (30 January 2007)
Platform secures network device development
Platform delivers industry advancements in secure communications and access that allow networking equipment developers to secure their devices and the information flowing through them. Brochure available
News from Green Hills Software (29 January 2007)
Thermal design software in running for award
Flo/PCB thermal design software is one of only three finalists in the PCB Design Tools category of their prestigious 2007 DesignVision Awards. Brochure available
News from Flomerics (29 January 2007)
EDA library supports RF design
AVX has developed a new software product library for use with Agilent's Advanced Design System (ADS). Brochure available
News from AVX (29 January 2007)
DSP design software puts comms on FPGAs
The latest release of the Synplify DSP software, v3.2, adds several IP blocks that are fundamental to wireless communications algorithms.
News from Synplicity (26 January 2007)
Router improves design and manufacturability
User application article STMicroelectronics has taped out a 65nm next-generation mixed-signal communications design using the Cadence Space-Based Router.
News from Cadence Design Systems (26 January 2007)
Compiler improves timing on large ASIC blocks
User application article Renesas Technology Corp has adopted Cadence Encounter RTL Compiler with advanced global synthesis in its ASIC design kits and methodologies for 90nm and below.
News from Cadence Design Systems (25 January 2007)
Software configuration management comes to Sydney
Perforce Software is continuing to expand in the Asia-Pacific region with the opening of a new office in Sydney, Australia.
News from Perforce Software (25 January 2007)
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