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Design and Development Software
Archive page 23 of 220
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PCB design and simulation go hand in hand
Saber Simulator and CR-5000 System Designer work together to deliver a platform for integrated system level electronic design, simulation and verification.
News from Synopsys ( 1 June 2007)
Framework enables design re-use at STM
User application article A custom IP-Xact framework developed by MDS enables STMicroelectronics to integrate all its system platform technologies into a consistent environment.
News from Magillem Design Services (31 May 2007)
Clock tree synthesis and optimisation unite
User application article PowerCentric brings together unique algorithms for clock tree buffering, gate-level clock gate logic synthesis and statistical average-case dynamic power analysis.
News from Azuro (31 May 2007)
Spacing-centric routing to exploit market demand
Nanovata Design Automation is developing a new generation of shape-based IC routing technology.
News from Nanovata Design Automation (31 May 2007)
Networking platform supports IP routing
Green Hills Software now supports NextHop Technologies' GateD advanced layer 3 IPv4 and IPv6 routing software with its Software's Platform for Secure Networking (PSN). Brochure available
News from Green Hills Software (31 May 2007)
Infineon and Chartered use litho-friendly design
User application article Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology.
News from Mentor Graphics UK (31 May 2007)
Workbench standardises automotive design
Tools package allows developers to use a C/C++ compiler for Renesas R32C designs, with advanced features particularly suited to automotive applications. Brochure available
News from IAR Systems (30 May 2007)
Methodology combines design with verification
User application article Fujitsu Kyushu Network Technologies is using the Cadence Incisive plan-to-closure methodology for SystemVerilog verification in RTL logic design teams.
News from Cadence Design Systems (30 May 2007)
Prototyping accord aids automotive development
Virtual prototypes of Renesas' high-performance processor platforms will help automotive developers with software development, architectural analysis and system verification.
News from Vast Systems Technology (29 May 2007)
EDA tools target complexity at 65nm and below
Upgraded netlist reduction and interconnect analysis tools help IC designers to optimise post-layout simulations, to maintain verification accuracy and to meet time to market goals.
News from Edxact (29 May 2007)
EDA tool stands test of comparison
Tool can compare any two layout and/or mask databases, which may be in different formats, have different hierarchies or come from different sources.
News from Softjin Technologies (29 May 2007)
CANopen development accelerated
Improved Windows-based software package speeds development of CANopen applications.
News from Ixxat (29 May 2007)
Software extends focus to IC-package codesign
Software combines core switching, power delivery network, I/O subsystem and package/PCB models in a single environment for accurate IC-package codesign.
News from Apache Design Solutions (29 May 2007)
Topographical technology speeds cameras to market
User application article Casio has adopted Synopsys Design Compiler topographical technology to shorten the design schedule for its next generation Exilim digital camera chips.
News from Synopsys (29 May 2007)
Linux platform set for automotive standard
Platform is chosen for developing vehicle onboard equipment for proof-of-concept activities.
News from Wind River Systems (29 May 2007)
Collaboration to improve ASIC verification
Synopsys and Synplicity have agreed to work together on next-generation high-performance verification solutions for ASIC designers.
News from Synplicity (28 May 2007)
Synthesisable building blocks jumpstart designs
The latest version of Cynthesizer is billed as the first high-level synthesis product to offer a direct path from high-level SystemC to GDSII.
News from Forte Design Systems (28 May 2007)
ASIC verification nears full device speed
Software offers full visibility into FPGA-based ASIC and ASSP prototypes enabling designers to find, fix and verify functional errors at speeds approaching that of the final device.
News from Synplicity (28 May 2007)
Mixed-signal flow is proved with UWB transceiver
Mentor Graphics has set up a new reference flow for analogue and mixed-signal SoC designs.
News from Mentor Graphics UK (24 May 2007)
Alliance marries FPGA design and verification
A new partnership between Zuken and Aldec aims to make it easier for designers to work with programmable devices. Brochure available
News from Zuken (24 May 2007)
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