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News Release from: Accellera
Edited by the Electronicstalk Editorial
Team on 25 October 2001
Latest Verilog standard released
IEEE 1364-2001, the Verilog hardware description language (HDL) standard, also known as Verilog-2001, was approved by the IEEE as a revised standard in March of this year.
IEEE 1364-2001, the Verilog hardware description language (HDL) standard, also known as Verilog-2001, was approved by the IEEE as a revised standard in March of this year This new standard description is now available from the IEEE, and supersedes the original 1995 standard
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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To improve design accuracy and address the needs of submicron designers, IEEE-1364 or Verilog-2001 adds capabilities for system-level modelling and greater ASIC timing accuracy.
Enhancements in the Verilog Programming Language Interface (PLI) provide greater simulation control and improved interoperability.
"IEEE 1364-2001 has the needed features required for next generation design starts and the official approval of the IEEE", said Dennis Brophy, Accellera chairman.
"Accellera is proud to support the development and enhancement of IEEE hardware description language standards".
"It gives me great pleasure to see Verilog reaffirmed as an IEEE standard.
Verilog is the most popular signoff language for electronic designs, and thanks to worldwide support from leading companies, it continues to gain users", commented Maq Mannan, IEEE 1364 chairman.
IEEE 1364-2001 improvements include: behavioural extensions so designers can model at a higher level and create code faster; ASIC timing modelling improvements enable more accurate signoff for deep submicron design; simulation control capabilities for performance improvement and for handling the system architecture of larger and more complex designs; and new and enhanced PLI routines for improved design tool interoperability.
The pdf version of the IEEE Standard 1364-2001 is available now from www.ieee.org.
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