Product category:
Recruitment, Reports and Resources
News Release from: Accellera
Edited by the Electronicstalk Editorial
Team on 29 March 2002
SDF gains IEEE approval
Accellera's Standard Delay Format (SDF) has been approved as IEEE Standard 1497-2001, and is now available from the IEEE.
Accellera's Standard Delay Format (SDF) has been approved as IEEE Standard 1497-2001, and is now available from the IEEE SDF allows for better EDA tools interoperability
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
Related stories
Engineers and technicians must be trained
Leading UK engineering and technology firms, with a combined multi-million pound spend on training and development, will assemble at the IEE 'Investing in Technical Teams' forum on 4 November 2004.
Workshop gives complete picture on CE.NET 5.0
A UK-based workshop will give embedded software development engineers hands-on experience in running the new 5.0 release of Windows CE.NET on next generation processors.
SDF is widely used to communicate timing information and constraints among various EDA tools.
It represents and interprets timing data for use at any stage of the electronic design process.
ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high-level technology parameters.
"Accellera collaborates with the IEEE, a leading international standards organisation to demonstrate our commitment to enhance language-based design", remarked Dennis Brophy, Accellera chairman, and director of strategic business development at Model Technology.
"Because of the important of EDA tool interoperability, SDF has become one of the most important HDL standards used by designers today".
SDF was first introduced into the EDA marketplace in 1991 by Cadence Design Systems.
Cadence placed SDF in the public domain in 1992 when it turned control over to Open Verilog International (OVI), now know as Accellera.
Accellera delivered the first SDF standard, version 2.0, in June 1993 (SDF version 1.0 was used by Cadence).
Accellera has since introduced version 2.1 in February 1994, and version 3.0 in May 1995.
Accellera subsequently turned over the standard to the IEEE that resulted in this standard.
In addition to its use with the Verilog HDL, VHDL (IEEE 1076) also takes advantage of SDF through the VITAL standard (IEEE 1076.4).
IEEE 1076.4-2001 VITAL specifically references the IEEE 1497-2001 version of the standard.
The SDF modelling standard is available now from the IEEE (www.ieee.org) for $80.00 (US) or $64.00 (US) for IEEE members.
• Accellera: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
