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News Release from: Accellera
Edited by the Electronicstalk Editorial
Team on 05 March 2003
Seminar to update SystemVerilog
Accellera is hosting a free SystemVerilog seminar this Thursday in Munich, Germany.
Accellera is hosting a free SystemVerilog seminar this Thursday in Munich, Germany This seminar will cover technical details about SystemVerilog, the first hardware design and verification language (HDVL), and the progress being made on standardisation
The tutorials cover using SystemVerilog for design and updates about the SystemVerilog committee's work and progress on assertions, testbench modelling, and C application programming interfaces (APIs).
The seminar will also include discussions of practical applications of these mechanisms for concise hardware design, integrated verification and assertion methodology and system interconnect.
The seminar will run from 9:00 to 13:00 on Thursday 6th March 2003 in Room 21B at the International Congress Centre Munich (ICM), Messe Munich, Germany.
Attendance is free, and no advance registration is required.
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