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News Release from: Accellera
Edited by the Electronicstalk Editorial
Team on 10 June 2003
Standards for language-based design
verification
Accellera has approved four new standards for language-based design verification.
Accellera has approved four new standards for language-based design verification The new Accellera standards include Property Specification Language (PSL) 1.01, Standard Co-Emulation Application Programming Interface (SCE-API) 1.0, SystemVerilog 3.1 and Verilog-AMS 2.1
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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Accellera's standards improve the way designers will design electronic circuits and systems in the 21st century.
"Today's announcement is an exciting milestone for Accellera and system-level verification", said Accellera Chairman Dennis Brophy.
"Accellera members and technical teams have done an outstanding job of getting these new language-based standards approved and ready for deployment".
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Accellera's PSL was developed to address the shortcomings of natural language forms of specification.
It gives the design architect a standard means of specifying design properties using a concise syntax with clearly defined formal semantics.
Similarly, it enables an RTL implementer to capture design intent in a verifiable form, while enabling the verification engineer to validate that the implementation satisfies its specification with dynamic (that is, simulation) and static (that is, formal) verification.
It also provides a standard means for hardware designers and verification engineers to rigorously document the design specification.
"A change is taking place in the way we design and verify our designs that will revolutionise the industry and result in the equivalent of a synthesis productivity breakthrough in verification.
This change demands that we move from natural language forms of specification to forms that are mathematically precise and verifiable, and lend themselves to automation.
The PSL 1.01 standard offers an opportunity to enable this huge leap in productivity of specification, design, and verification", said Harry Foster, Accellera Formal Verification Technical Committee Chair.
The SCE-API standard defines a high-speed, asynchronous, transaction-level interface between simulators or testbenches and hardware-assisted solutions such as emulation or rapid prototypes.
"The SCE-API offers an intelligent interface for many types of tools", noted Brian Bailey, Accellera Interfaces Committee Chair.
"Since verification requirements are increasing, in many cases, a single tool isn't enough.
In these cases, a standard interface between the tools can bring the best in class tools together, and allow for better re-use of models among different design tools".
SystemVerilog 3.1 evolves the Verilog language with powerful design and verification capabilities.
It provides design constructs for architectural, algorithmic and transaction-based modelling.
It adds an environment for automated testbench generation, while providing assertions to describe design functionality, including complex protocols, to drive verification using simulation or formal verification techniques.
Its C-API provides the ability to mix Verilog and C/C++ constructs without the need for PLI for direct data exchange.
"SystemVerilog 3.1 is a monumental effort that breaks new ground for the electronics industry and nanometer verification challenges", said Vassilios Gerousis, Accellera's Technical Committee Chairman.
"It is the first hardware design verification language or HDVL standard, built on top of Verilog HDL.
It was developed and approved through the cooperation of EDA companies and users alike, with more than 40 worldwide industry experts and 120 contributors".
Gerousis added, "SystemVerilog 3.1 is ready for early adoption by EDA companies and customers".
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