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Product category: Recruitment, Reports and Resources
News Release from: Accellera
Edited by the Electronicstalk Editorial Team on 15 October 2003

IEEE endorses Accellera standards

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Accellera's Advanced Library Format (ALF) has been approved as IEEE1603-2003.

Accellera's Advanced Library Format (ALF) has been approved as IEEE1603-2003 In addition, the VHDL and Verilog RTL synthesis standards have passed balloting and are now IEEE1076.6-1999 and IEEE1364.1-2002, respectively, and IEEE1076-2002 (VHDL) adds new features

These IEEE standards improve nanometre design library descriptions and tools, Verilog and VHDL and synthesis.

"Accellera's objective is to have the IEEE formalise and certify all our standards", noted Dennis Brophy, Accellera Chairman.

"The ALF standard and the Verilog and VHDL standard improvements are examples of how Accellera's members work with and support the leading international electronics standards body to improve the IC design process".

IEEE1603 standardises the language and semantic representation for design libraries.

It supports an RTL to GDSII descriptions of functional, electrical performance and layout views for technology libraries, scalable from cells to complex hierarchical design blocks.

The ALF effort was started in 1996.

ALF was released as an Accellera standard in 2000.

Accellera assigned the ALF copyright to the IEEE in 2001, and ALF became an IEEE project.

The objective was to create a standard that addresses long-term library modelling requirements for next-generation EDA applications and maintain compatibility and interoperability with existing library formats and development practices.

The IEEE1076.6 and 1364.1 (Verilog and VHDL RTL) synthesis standards define the syntax and semantics that can be used by all compliant RTL synthesis tools to achieve uniformity and interoperability.

The IEEE1076 standard includes three enhancements.

The definition of concatenation and real types improves portability among tools.

VHDL now supports multibyte characters within comments.

This allows users to document their designs in their native language, such as Japanese, Korean and Chinese.

Buffer mode ports are improved so that they can be easily used with out or in-out mode ports.

When designing library components or designing a block that uses library components, this change makes it easy to use a single coding style (single port type) that can be used in any context.

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