Product category:
Recruitment, Reports and Resources
News Release from: Accellera
Edited by the Electronicstalk Editorial
Team on 30 October 2003
Brophy reveals plans for standardisation
Dennis Brophy has been re-elected Chairman of Accellera for a fourth term.
At recent elections, Dennis Brophy, Director of Strategic Business Development at Model Technology, was re-elected Chairman of Accellera for a fourth term Shrenik Mehta, Director, Frontend Technologies - ASICs and Processors, Sun Microsystems, was re-elected Vice Chair
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
Related stories
Engineers and technicians must be trained
Leading UK engineering and technology firms, with a combined multi-million pound spend on training and development, will assemble at the IEE 'Investing in Technical Teams' forum on 4 November 2004.
Workshop gives complete picture on CE.NET 5.0
A UK-based workshop will give embedded software development engineers hands-on experience in running the new 5.0 release of Windows CE.NET on next generation processors.
Dave Kelf, Vice President of Marketing, Novas Software, has been elected Treasurer.
Karen Bartleson, Director of Interoperability, Synopsys, was re-elected Secretary for a fourth term.
"Our members - semiconductor companies, electronic system designers and electronic design automation solution suppliers - work together to create standards that address design complexity and improve the way designers create electronic circuits and systems, and I am pleased to continue as Accellera's chair to help the organisation deliver on its goals", remarked Brophy.
In the coming year, Accellera plans to enhance the process it uses to build and maintain electronic design standards with the IEEE and assign the copyright of SystemVerilog 3.1a to the IEEE for standardisation consideration by the IEEE1364 Working Group before the 41st Design Automation Conference.
Accellera's technical committees have plans in place to complete the unification of Accellera's Property Specification Language (PSL) with SystemVerilog 3.1 assertions to produce PSL 1.1, and synchronise the Accellera Verilog Analog/Mixed Signal (Verilog-AMS) design language standard with its SystemVerilog syntax.
Accellera also looks forward to another successful Design Verification Conference in March 2004.
• Accellera: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page

