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Exhibitions, Courses, Conferences and Training
News Release from: Accellera
Edited by the Electronicstalk Editorial
Team on 27 November 2003
SystemVerilog explained at Santa Clara
symposium
Accellera is to host a SystemVerilog symposium and vendor fair on Thursday 4th December 2003 in Santa Clara, California.
Accellera is to host a SystemVerilog symposium and vendor fair on Thursday 4th December 2003 in Santa Clara, California The SystemVerilog symposium will features two tracks: one on SystemVerilog basic training, presented in a designer-centric fashion by Verilog design expert, Cliff Cummings of Sunburst Design; and the second is a SystemVerilog product technology track comprising presentations from leading electronic design automation solution suppliers
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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Engineers and technicians must be trained
Leading UK engineering and technology firms, with a combined multi-million pound spend on training and development, will assemble at the IEE 'Investing in Technical Teams' forum on 4 November 2004.
Accellera committee members will present updates on current SystemVerilog activities.
Lunch will be served during this session.
The EDA vendor fair is a 2-hour event during which participating companies will demonstrate their SystemVerilog-based products and be available to discuss their SystemVerilog support.
Accellera Technical Chair Members will also be available for private discussions.
Demos of SystemVerilog-based tools from leading EDA companies will include Accellera members Axis Systems, Cadence, Mentor Graphics, Novas, Real Intent and Synopsys.
The event will be held at the Santa Clara Marriott, 2700 Mission College Blvd, Santa Clara, California, starting with registration and breakfast at 0815 PDT.
Delegates can register on the Accelera website.
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