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News Release from: Accellera
Edited by the Electronicstalk Editorial
Team on 15 May 2007
Board sets the standard in verification
The Accellera Board of Directors has approved the SCE-MI 2.0 specification as an Accellera verification standard.
The Accellera Board of Directors, representing systems, semiconductor and design tool member companies, has approved the Standard Co-Emulation Modelling Interface (SCE-MI) 2.0 specification as an Accellera verification standard A previous version of the standard, SCE-MI 1.1, was approved by the Accellera Board in April 2005
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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The work on the standard was done by Accellera's Interface Technical Committee (ITC).
"SCE-MI 2.0 provides an easy way to connect and migrate transactor models between simulation, emulation and rapid prototyping environments", notes Accellera Chair, Shrenik Mehta.
"With it, SoC design and verification teams are seeing improved electronic design productivity, and the new SCE-MI standard makes it more worthwhile for developers to support SCE-MI-based models".
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"We are pleased to see the acceptance of the SCE-MI 2.0 draft specification", adds Brian Bailey, Chair of Accellera's Interface Technical Committee (ITC).
"Vendors are now working on their implementations which will provide additional capabilities for faster and more effective testbenches with hardware assisted solutions".
"We will continue to look for ways in which we can enhance the performance and usability of multi-tool verification solutions".
SCE-MI 2.0 adds a new use model built on a subset of the SystemVerilog Direct Programming Interface (DPI) for future convergence, and it is now compatible with the Open SystemC Initiative (OSCI) Transactor Level Modelling (TLM) definition.
The new Accellera standard maintains backward compatibility with the previous version.
It also has added improvements such as a streaming interface with data shaping to optimise emulation speed, increased options for model migration from simulation to emulation and vice versa, as well as more simplified transactor modelling.
Overall, these enhancements improve designer productivity and model portability for transaction-level verification on heterogeneous platforms.
The SCE-MI standard improves high speed transaction-level verification between different hardware and software simulation and emulation systems.
To support designers and encourage continued adoption, it improves model portability between different verification acceleration tools.
In the near term, a working example will be released for using the standard and dealing with any portability issues that surface during vendor implementation.
The ITC committee will also work on broadening the specification to include additional languages and constructs to stay ahead of the increasing challenges in functional verification.
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