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Product category: Design and Development Software
News Release from: Actel Europe | Subject: Libero
Edited by the Electronicstalk Editorial Team on 20 June 2001

Libero sweeps up full set of FPGA design
tools

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Libero is Actel's next-generation integrated design environment for field-programmable gate array (FPGA) development and design.

Libero is Actel's next-generation integrated design environment for field-programmable gate array (FPGA) development and design A comprehensive design management environment, Libero integrates industry-leading design tools and streamlines the design flow; manages all design, run and report files; and passes necessary design data between tools

The Libero tool suite is available to FPGA designers through a robust, easy-to-navigate graphical user interface.

Libero includes best-in-class tools such as Innoveda's DxViewDraw schematic capture tool; SynaptiCAD's WaveFormer Lite test bench generation system; Model Technology's ModelSim simulation and design verification software; Synplicity's Synplify 6.2 synthesis software; and Actel's Designer Series place-and-route software and Silicon Explorer verification and logic analyser tool.

"Libero takes Actel's tool offerings to the next level with the integration of tools from Innoveda, SynaptiCAD, Model Technology and Synplicity", said Dennis Kish, vice president of marketing at Actel.

"A flexible and easy-to-use design environment, Libero enables designers to bring products to market faster with dramatically improved quality of results".

According to Kish, the improved quality of results stems directly from the best-in-class tools integrated from Actel and its leading EDA partners.

For example: S DxViewDraw is a schematic capture vehicle that includes mixed-language support (ie VHDL blocks and schematic symbols can be mixed).

S WaveFormer Lite is a test bench generation system that converts graphical stimulus files into HDL test benches and manages the multiple test benches required for different design configurations.

S ModelSim is a simulation tool offering source-level debug as well as VHDL and Verilog behavioural, structural and back-annotated dynamic simulation.

S Synplify is a synthesis solution enabling optimal mapping of VHDL and Verilog code to Actel FPGA devices.

S Designer Series tools deliver complex basic-block generation, automatic place-and-route with full support for pin fixing and assuring accurate characterised timing reports.

And S Silicon Explorer is a novel tool offering verification and real-time internal probing of the programmed device.

The Libero tool suite is available in three versions: Platinum, Gold and Silver.

Actel's Libero Platinum is a complete tool suite solution with unlimited design capacity and customer support.

For users designing system-level devices of 50,000 gates or less, Actel offers support with its Libero Gold version.

Libero Silver offers tool support from entry to programming for Actel devices of 10,000 gates or less, including Actel's eX family and the ProASIC A500K050.

Libero Silver does not include simulation, but designers may use their own simulator without restrictions or compatibility problems.

For current customers, Actel will continue to support its DeskTOP tools for an additional 15 months.

Additionally, the company offers a migration path option from Actel's DeskTOP tools to the Libero tool suite at no charge to customers on maintenance.

Libero Platinum is priced at $2,495 with maintenance of $1,996 per year.

Libero Gold is priced at $995 with maintenance of $796 per year.

Libero Silver will be offered at no charge to qualified designers for one year.

A Libero Platinum evaluation version may be used for 45 days free of charge.

It includes all the integrated tools, functionality and power of Platinum without the programming capability.

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