Product category:
Programmable Logic Devices
News Release from: Actel Europe | Subject: Military-spec Axcelerator FPGAs
Edited by the Electronicstalk Editorial
Team on 31 October 2003
FPGAs get into military trim
The high-performance, nonvolatile Axcelerator family of FPGA devices has been qualified to military specifications.
The high-performance, nonvolatile Axcelerator family of FPGA devices has been qualified to military specifications The Axcelerator devices are the first FPGA family, with flexible soft IP implementing 66MHz PCI and 1Gbit/s Fibre Channel designs, to meet performance specifications over the full military temperature range (-55 to +125C)
This article was originally published on Electronicstalk on 5 Aug 2008 at 8.00am (UK)
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The single-chip AX2000, AX1000, AX500 and AX250 devices are now available in three new packaging and screening options - military-temperature plastic (MTP), military-temperature hermetic (MTH) and hermetic packaging fully screened to MIL-STD 883 class B (883B) - offering densities up to two million system gates and up to 288Kbit memory.
The Axcelerator family's signature features of industry-leading performance, low-power, design security and firm-error immunity make the new devices suitable for an array of military and avionics applications requiring high bandwidth, such as radar, communications and weapons systems.
The Axcelerator devices feature up to 684 I/Os and are supported by a broad portfolio of IP, including 66MHz PCI and 1Gbit/s Fibre Channel.
Further reading
FPGA family promises more for less
Low-power field-programmable gate arrays claim the industry's best power-, area-, logic- and feature-per-I/O ratios in a programmable device.
Programmable devices add ADC calibration
Fusion PSC calibration intellectual property eliminates the additional discrete ADCs and prescalers often required to achieve higher levels of accuracy.
Through internal benchmarks using these high-performance IP cores, Actel has verified that the Axcelerator devices can deliver the industry's highest performance for military-grade FPGAs.
Built on the company's AX architecture, the antifuse-based Axcelerator family delivers better than 500MHz internal operation and up to 100% resource usage.
Additionally, the company's live at power-up, single-chip Axcelerator FPGAs avoid inrush current spikes, simplify system power supply design and generally offer lower standby and dynamic power consumption than competing solutions.
The devices offer levels of design security beyond SRAM-based offerings and conventional ASIC solutions, enabling designers to safeguard against common security problems, including overbuilding, cloning, reverse engineering and denial of service.
Firm errors, which occur when high-energy neutrons generated in the upper atmosphere strike the configuration cells of SRAM-based FPGAs, can be impossible to prevent.
Because the antifuse configuration cannot be altered once programmed, firm errors in Axcelerator FPGAs are nonexistent.
Fully qualified AX2000, AX1000, AX500 and AX250 devices in MTP packaging are available now with pricing beginning at $260 in 5000-unit quantities.
The AX2000, AX1000, AX500 and AX250 devices in MTH packaging will be available in Q1 2004 with pricing beginning at $430 in 5000-unit quantities.
In addition, 883B Axcelerator products will start shipping in Q2 2004 with pricing beginning at $770 in 5000-off units.
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