Product category:
Design and Development Software
News Release from: Actel Europe | Subject: Libero 6.1
Edited by the Electronicstalk Editorial
Team on 25 January 2005
IDE takes on latest budget Flash FPGA
designs
Actel's new Libero 6.1 integrated design environment (IDE) provides complete support for the company's new Flash-based ProASIC3 and ProASIC3E devices.
Actel's new Libero 6.1 integrated design environment (IDE) provides complete support for the company's new Flash-based ProASIC3 and ProASIC3E devices The Libero 6.1 IDE contains a range of performance, resource optimisation and ease-of-use features that, combined with leading third-party design tools, deliver an efficient, seamless flow through simulation, synthesis and place-and-route
This article was originally published on Electronicstalk on 13 May 2008 at 8.00am (UK)
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The software is optimised to exploit the architectural features of the ProASIC3 and ProASIC3E devices, including the unique on-chip FlashROM (FROM), which can easily be programmed independent of the FPGA core.
"As the industry's first FPGAs with on-chip FlashROM and a host of advanced features, the ProASIC3/E devices offer designers an unprecedented level of functionality at an extremely low price point", said Saloni Howard-Sarin, Director of Antifuse and Tools Marketing at Actel.
"We have extensively tested this enhanced tool suite over several months to ensure that Libero IDE 6.1 addresses and exploits all of the silicon features in a robust and intuitive design environment".
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"In turn, our customers can achieve optimised performance for these next-generation devices with complete confidence".
The Libero IDE applies innovative new technology to help designers take advantage of the FROM function of the ProASIC3/E devices, which can be easily programmed independent of the FPGA core for applications such as device serialisation, Internet Protocol (IP) addressing and version control.
A new FlashPoint programming file generator integrates preset FROM macros including device serialisation, allowing customers to merge the FPGA configurations and the FROM programming file.
The FlashPoint programming file generator also enables all encryption capabilities for the FROM contents, such as security header, encryption key and FlashLock security.
Using the FlashPoint software, designers can change the functionality of the FROM after the completion of the ProASIC3/E design process while preserving the security of the ProASIC3/E core logic.
Actel's ACTgen core builder now provides a comprehensive user interface to ensure simple implementation and seamless flow of various FROM content options into the hardware description language (HDL).
Custom FROM applications can be input via a data table or read as a text file.
Users can also specify a built-in feature that provides auto increment or decrement during the programming process.
This enables each device to have a unique serial number for specialised applications.
The ACTgen core builder has a new "Visual PLL" interface that provides a wide range of PLL programming options to dramatically ease the setting of accurate PLL parameters.
Using customisable clock conditioning circuitry in the PA3/E devices, the designer can adjust frequency and feedback settings, and set various detailed parameters for clock applications via "tailor-made" PLL schematics.
The Libero 6.1 IDE includes a MultiView Navigator I/O attribute editor that enables easy selection and programming of up to 19 I/O standards within ProASIC3/E devices, thereby streamlining the physical implementation process.
The tool suite offers complete support for the high-speed ProASIC3/E VersaNet global network to allow mapping for up to 252 different internal or external clocks within the ProASIC3/E FPGAs.
The ChipPlanner, Physical Design Constraints (PDC) and Magma Palace (Physical and Logical Automatic Compilation Engine) physical synthesis tools provide full support of VersaNet global networks, thus simplifying the use of all physical constraint flows.
Libero 6.1 timing driven place and route, coupled with Synplicity's Synplify and Magma's Palace tools, ensure PA3/E product performance of 66MHz, 64bit PCI performance - the highest level of performance for any value-based FPGA.
The Actel Libero 6.1 IDE is available in three editions: Platinum, Gold and Silver.
The Platinum version sells for $2495, the Gold version sells for $595 and Silver is a free version.
All are one-year renewable licences.
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