Product category:
Design and Development Software
News Release from: Actel Europe | Subject: Libero version 6.2
Edited by the Electronicstalk Editorial
Team on 14 July 2005
FPGA design suite gets to grips with
timing
A new integrated design environment integrates best-in-class design tools to enable FPGA designers to achieve the highest results in terms of quality, efficiency and functionality.
Detailing significant new functionality for design analysis and timing closure, Actel has introduced its Libero version 6.2 integrated design environment (IDE), which integrates best-in-class design tools to enable field-programmable gate array (FPGA) designers to achieve the highest results in terms of quality, efficiency and functionality With Libero 6.2, Actel unveils its new SmartTime static timing analysis environment, enabling customers to analyse and manage timing constraints, perform advanced timing verification, and ensure predictable timing closure through a tight integration with timing-driven place and route
This article was originally published on Electronicstalk on 13 May 2008 at 8.00am (UK)
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In addition, the Libero 6.2 IDE includes enhanced synthesis capabilities from Synplicity and physical synthesis features from Magma Design Automation.
Further, Libero now runs on Linux and Solaris platforms.
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SmartTime is a powerful new multi-view product developed by Actel to help designers perform detailed timing analysis and quickly determine the steps necessary to achieve design closure.
The SmartTime Constraints Editor view enables users to list, edit and create precise timing constraints.
It includes a graphical user interface with visual dialogs that guide users toward capturing their timing requirements and timing exceptions correctly.
Another view, the SmartTime Analyzer, allows designers to perform per-clock-domain minimum and maximum timing analysis, and provides inter-clock domain analysis capabilities.
The tool simplifies the analysis process by enabling designers to track paths with timing violations quickly.
Designers can then directly set specific timing exceptions on the violating paths to tighten or relax the requirements and quickly iterate toward timing closure.
Mentor Graphics' ModelSim is a leading Windows-based simulator for VHDL, Verilog or mixed-language simulation environments.
The integrated ModelSim verification and debug environment, which helps designers locate bugs faster, is being offered with unlimited availability to all Actel customers for the first time.
Synplicity's industry-leading Synplify FPGA synthesis software offers a new capability to forward annotate Synopsys Design Constraints (SDC) and physical constraints, enabling the Libero 6.2 IDE to import user-defined constraints automatically then manage, track and pass them forward to design implementation, enabling designers to meet timing closure rapidly.
In addition, the software now includes critical path resynthesis to improve quality of results (QoR) for designs based on Actel's Axcelerator family of FPGAs.
Magma Design Automation's Palace physical synthesis software now also provides support for Actel's Axcelerator family.
The fully automated Palace software features advanced technologies such as multi-clock retiming, architecture-specific mapping, and constraint-driven and placement-guided optimisation.
The Actel Libero 6.2 IDE is available in a Platinum edition on Windows and Unix platforms, which sell for $2495 and $4995, respectively.
Libero 6.2 IDE is available also on Windows in a Gold edition, which is free.
All editions are one-year renewable licences.
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