Product category:
Programmable Logic Devices
News Release from: Actel Europe | Subject: Libero 6.3 software
Edited by the Electronicstalk Editorial
Team on 09 November 2005
Secure design flow for complex FPGA
development
The latest version of Libero 6.3 software provides a secure design flow for integrating Actel's CoreMP7, the soft ARM7 family processor, into Actel's non-volatile field-programmable gate arrays.
The latest version of Libero 6.3 software provides a secure design flow - from synthesis through implementation - for integrating Actel's CoreMP7, the industry's first soft ARM7 family processor, into Actel's single-chip, non-volatile field-programmable gate arrays (FPGAs) With this software release, Actel builds on the capabilities of its industry-leading SmartTime static timing analysis environment to deliver enhanced minimum-delay support, uniquely enabling precision hold-time characterisation for high-speed FPGAs
This article was originally published on Electronicstalk on 13 May 2008 at 8.00am (UK)
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The enhanced software also automates the task of I/O voltage assignment and supports Actel's new RTAX4000S devices, the industry's highest density FPGA for space applications.
"Combining best-in-class third-party EDA tools with Actel's proprietary design tools, the Libero 6.3 IDE continues Actel's tradition of delivering an unmatched level of value with a feature-rich tools suite", said Michael Mertz, Senior Manager of Tools Marketing at Actel.
"By enhancing Libero to support a soft ARM7 family processor implementation, we can put this advanced microprocessor technology into the hands of more FPGA designers".
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"Furthermore, by automating previously manual tasks and offering unique timing analysis capabilities, we enable FPGA designers to quickly achieve optimal results".
Optimised to support CoreMP7, Libero 6.3 provides an advanced block-level methodology that enables designers to aggregate IP around CoreMP7, and map it into Actel's ProASIC3/E FPGA fabric with predictable timing and verify operation.
Tight integration with industry-leading, third-party tools from Magma Design Automation, Mentor Graphics and Synplicity enables seamless synthesis, verification and physical synthesis for designs incorporating CoreMP7.
Enhanced black-box support from Synplicity and Magma Design Automation, within their respective synthesis and physical synthesis tools, enable a secure flow, while Actel's own proprietary tools provide encryption to protect the valuable ARM7 IP from unauthorised access.
Actel's tools also deliver the timing analysis and layout functionality necessary to simplify and accelerate system design using CoreMP7.
Unlike SRAM-based devices, Actel's impenetrable Flash architecture and powerful encryption techniques safeguard ARM7 and user IP against reverse engineering or theft, helping to preserve a company's competitive advantage and protect its development investment.
Delivering this unique, end-to-end secure flow for Actel devices, Libero 6.3 enables the first ARM processor-based technology for implementation on programmable logic as a soft IP core.
As a result, designers can build cost-effective solutions for a variety of value-based consumer, industrial, automotive and high-reliability applications.
With advanced features and new device support Libero 6.3 delivers enhanced timing and layout capabilities that promote better design practice and designer efficiency.
Actel's industry-leading SmartTime timing analysis environment now features 'Enhanced_Min_Delay', (EMD) characterisation, a comprehensive process that, for the first time, brings precise hold-time analysis to the realm of FPGA design.
EMD eliminates the need to over-guardband a design for minimum delay, improving time-to-design closure.
This significant enhancement gives SmartTime users a more comprehensive way to verify set-up and hold timing at the internal and chip-to-chip level.
Libero 6.3 also employs advanced matching algorithms to automate I/O voltage assignments, alleviating the time-consuming process of optimising I/O schemes for complex, processor-based designs.
This new I/O bank assigner automatically assigns VCCI voltages and VREF pins to appropriate unassigned I/Os during layout.
Automating this previously manual process simplifies FPGA design, especially for complex devices containing as many as 80 different types of I/Os.
Further, Libero 6.3 delivers the tools necessary to target, layout and verify the next-generation of high-reliability space designs using Actel's new RTAX4000S device.
At four million system gates, the RTAX4000S device is the industry's highest density radiation-tolerant FPGA.
The Actel Libero 6.3 IDE is available in a Platinum edition for Windows and Unix platforms, which sell for $2495 and $4995 respectively.
A free Gold edition is also available for Windows.
All editions are one-year renewable licenses.
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