Product category:
Programmable Logic Devices
News Release from: Actel Europe | Subject: ProASIC3L
Edited by the Electronicstalk Editorial
Team on 08 January 2008
FPGAs cut both static and dynamic power
Flash-based FPGA family combines dramatically reduced power consumption with up to 350MHz operation.
The ProASIC3L family of FPGAs from Actel Corporation is aimed at designers of high-performance power-conscious systems Featuring 40% lower dynamic power and 90% lower static power than its previous-generation ProASIC3 FPGAs, the new Flash-based family combines dramatically reduced power consumption with up to 350MHz operation
This article was originally published on Electronicstalk on 23 Apr 2001 at 8.00am (UK)
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First flash-based industrial-grade FPGAs
Actel is shipping the industry's first flash-based "live-at-power-up" FPGA devices qualified to industrial specifications.
Largest-yet claim for flash-based FPGAs
Actel is sampling the A500K180 and A500K270 flash-based ProASIC 500K gate FPGAs with 369,000 and 473,000 system gates, respectively.
As a result, designers in high-performance market segments, such as industrial, medical and scientific, now have access to flexible, feature-rich solutions that offer speed, low power and low cost.
The ProASIC3L family also supports the free implementation of an FPGA-optimised 32bit ARM Cortex-M1 processor, allowing system designers to select the Actel Flash-based FPGA solution that best meets their speed and power design requirements regardless of application or volume.
"The importance of power consumption is not a question, but a statement of fact", says Fares Mubarak, Senior Vice President at Actel.
Further reading
Libero sweeps up full set of FPGA design tools
Libero is Actel's next-generation integrated design environment for field-programmable gate array (FPGA) development and design.
FPGAs have hardened latches for space reliability
Actel has qualified and is shipping its RT54SX32S FPGA, the first member of its radiation-tolerant RTSX-S family specifically designed to address single-event upsets (SEUs) in space.
Libero sweeps up FPGA design software
Actel has enhanced its Libero integrated design environment for FPGA development and design.
"As process technology nodes shrank, static power became a major concern".
"However, over the past few years, Actel has dramatically reduced static power dissipation, allowing us to intensify our focus on dynamic power, which now accounts for a larger portion of the power budget".
"Actel's new ProASIC3L family offers the unique combination of low dynamic and static dynamic power with high performance".
Dynamic power is critical in applications where clocks are constantly switching and providing input to an FPGA, such as high-speed data pipelines for portable video and medical appliances.
Like the company's award-winning 5uW Igloo FPGA family, the ProASIC3L devices support a 1.2V core voltage and Actel's innovative Flash-Freeze technology.
Flash-Freeze enables designers to quickly switch the device from dynamic operation to static without switching off clocks or power supplies.
In a typical high-speed design, using comparable one-million gate FPGAs SRAM-based competitive solutions consume 60% higher dynamic power and 100 times more static power than the ProASIC3 devices, which consume just 100mA of dynamic power and 0.4mW of static power.
Based on Actel's successful ProASIC3 architecture, the ProASIC3L family comprises four devices ranging from 250,000 to three million gates: the A3P250L, A3P600L, A3P1000L and A3PE3000L.
Offered in both commercial and industrial temperature grades, the devices feature embedded SRAM memory, high I/O counts, phase-locked loops (PLLs) and nonvolatile memory.
Free of the licence and royalty fees typically associated with industry-leading processor cores, Actel is initially offering the 32bit ARM Cortex-M1 processor for use in its 600,000-gate ProASIC3L device, the M1A3P600L.
Operating at up to 70MHz and consuming 32% of available chip real estate, the highly configurable processor provides a good balance between size and speed, while offering space for customisation.
The ProASIC3L family is supported by the Actel Libero integrated design environment (IDE) version 8.2.
The Libero IDE includes sophisticated power-driven layout and analysis tools to further reduce dynamic power and provide users with a comprehensive understanding of power usage in all functional modes of a design.
By using power-driven layout rather than timing-driven layout, system designers can reduce dynamic power by as much as 30%.
Surpassing the knowledge and support offered for proprietary processors, the Cortex-M1 processor is supported by Actel as well as third-party tools from compilers and debuggers to RTOS support.
Actel supports the Cortex-M1 processor with the Actel Libero IDE as well as its CoreConsole and SoftConsole environments all available for free download from Actel's website.
Actel will offer ProASIC3L and an M1-enabled ProASIC3L starter kits to enable designers to quickly evaluate the family and prototype their low-power design.
Detailed current-monitoring capabilities allow users to directly measure the low current consumption and validate the design's performance when using ProASIC3L or M1-enabled ProASIC3L devices.
The ProASIC3L family is sampling now.
Pricing for the ProASIC3L family, including the M1-enabled devices, starts at US $3.95 in volume.
The M1A3P600L will also be available in Q1 2008 with the three remaining M1-enabled family members slated for Q2 and Q3 2008.
Version 8.2 of the Actel Libero IDE will be available in Jan 2008.
The two ProASIC3L starter kits will be available in Q1 2008.
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