Product category:
ATE Systems
News Release from: Advantest (Europe) | Subject: Failure Diagnostics
Edited by the Electronicstalk Editorial
Team on 29 May 2002
Failure diagnostics under development
Advantest is to develop a fast, accurate failure diagnostics solution for deep-submicron high-speed SoC designs leveraging TetraMax automatic test pattern generation technology from Synopsys.
Advantest Corp is to develop a fast, accurate failure diagnostics solution for deep-submicron, high-speed SoC designs leveraging TetraMax automatic test pattern generation (ATPG) technology from Synopsys Currently under development, Advantest's SoC failure diagnostics tool will use data communication between the company's T6000 series ATE system and Synopsys' TetraMax ATPG tool to streamline the process of detecting failures in complex chips
This article was originally published on Electronicstalk on 11 May 2001 at 8.00am (UK)
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"SoC development is increasingly focused on reducing time to market, improving production margins, reducing design and manufacturing costs and implementing a design-for-test (DFT) methodology that reduces the overall cost of test", said Nick Konidaris, president and chief executive officer of Advantest America, "We are working closely with Synopsys to develop an SoC failure diagnostics tool that optimises and streamlines communication between our respective SoC-focused tools to help chipmakers attain these goals".
Today's SoC designs require far more complex failure diagnostics than ever before to bridge the technical gap between design and production-test teams, and to reduce the time engineers spend diagnosing a failure in engineering or manufacturing tests.
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Advantest's SoC failure diagnostics tool will transfer data on the location of the failure from the T6000 series ATE system to TetraMax, enabling TetraMax to use its failure diagnostic feature to identify the failure node, quickly pinpointing the problem.
The diagnostic tool with TetraMax support will be especially effective for scan-based design, the largest and most time-consuming part of any DFT methodology.
By automating the failure diagnosis process, the user can reduce the turnaround time of analysis for both the design and production-test teams.
"To ensure an optimal flow between Advantest's SoC failure diagnostics tool and TetraMax, Advantest is an active member of Synopsys' in-Sync program for EDA interoperability", said Karen Bartleson, Synopsys' director of quality and interoperability.
"Customers will benefit from a smooth, interoperable flow between Advantest and Synopsys tools that can help reduce their time to market".
In addition, Advantest has implemented these failure diagnostics methods on its e-beam test system.
Linking fault localisation information and design information will enable more precise and accurate failure area and defect factors to be specified.
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