Product category:
Programmable Logic Devices
News Release from: Altera Europe | Subject: HardCopy structured ASICs
Edited by the Electronicstalk Editorial
Team on 11 January 2005
Structured ASICs speed satellite modems
to market
Mark Vanderaar and Ganesh Narayanaswamy describe how HardCopy structured ASICs from Altera were used in a modem designed by Efficient Channel Coding for broadband Internet access through satellites.
Structured ASICs are a new class of devices that address the burgeoning costs of developing traditional ASICs and the time taken to obtain the first fully functional devices This article describes how HardCopy structured ASICs from Altera were used in the IPX-5100, a modem designed by Efficient Channel Coding (ECC) for broadband Internet access through satellites
This article was originally published on Electronicstalk on 26 Sep 2005 at 8.00am (UK)
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Structured ASICs aid modem design
HardCopy structured ASICs from Altera have been used in the IPX-5100, a modem designed by Efficient Channel Coding (ECC) for broadband Internet access through satellites.
Low-cost FPGA family available in production
Built on TSMC's 65nm low-power process, the Cyclone III family includes devices that are qualified for commercial, industrial and extended temperatures.
The IPX-5100 interfaces with conventional geostationary satellites as well as the new iPStar-1 satellite providing broadband access rates up to 8Mbit/s download and 4Mbit/s upload.
The IPX-5100 uses ECC's adaptive coding and modulation (ACM) technology to dynamically change the channel coding and modulation technique "on-the-fly" according to the time-varying channel conditions.
These methods dramatically improve the satellite system capacity by customising the link to an individual IPX-5100, allowing optimised use of the limited satellite bandwidth.
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User traffic can be transmitted in as high a modulation level in combination with as high a code rate as the instantaneous link condition allows and the strongest code and modulation should only be used to keep reliable data transmission when link is in worst condition.
Effectively, the adaptive scheme significantly improves the average information throughput per satellite transponder.
The result of these efforts is the first satellite ACM-enabled system, iPStar offered by Shin Satellite Public Company (Asia's second largest satellite system operator).
Due to efficiencies enabled by the combination of the iPStar-1 satellite (launched in late Spring, 2004) and the IPX-5100 ACM technology, the iPStar system can now provide broadband Internet connectivity to consumers and small-businesses competitively with cable modem and DSL services.
Initially the IPX-5100 modem was designed with an Altera FPGA to prototype and verify the functionality of ECC's ACM technology.
Additionally, using the prototype, ECC was able to field trial and qualify the IPX-5100 addressing the iPStar system requirements.
The next step was to move to a lower cost solution once field qualifications were approved and the terminal was ready for medium-volume production.
There are merits to considering up-front what devices to use beyond the prototyping phase.
An ASIC or a conversion ASIC (ASICs derived through conversion of an FPGA netlist) requires synthesis or resynthesis of the design, generating a netlist different than the one used to prototype.
This difference adds risk and could increase costs as well as impair market-entry plans for the product should the first silicon be not functional.
It would be nice to have a path to seamlessly migrate the prototype-proven netlist to a device suitable for high-volume production.
ECC evaluated various structured ASICs and conversion ASICs, but found that only HardCopy devices supported such a requirement.
The migration of the design from prototype to medium volume production was aided by pin-compatibility between FPGA and the HardCopy device.
Choosing the right I/O and package not only helped ECC to replace the FPGA with the HardCopy device, but also vastly eased the requalification of the IPX-5100 modem.
ECC used a combination of Altera's and third-party software to prototype the design, perform physical synthesis and static timing analysis, and generate the design database to transfer to Altera for migration to the structured ASIC.
Having an integrated design environment which supports synthesis and simulation tools allowed ECC to leverage their existing tool-suite and take the design from prototype to silicon in the quickest possible time.
Coding to synchronous design principles facilitated several design steps including synthesis, timing analysis and testability of the device.
While it is always enticing to get that extra megahertz through a code segment that violates these established rules, inadvertent usage can considerably hamper verification and testability issues.
ECC used the Design Assistant feature in Altera's Quartus II software to find any such violations in the design, make an analysis and fix if necessary.
Knowledge of such violations prior migration helped ECC to ensure that the design can be migrated smoothly in the quickest possible time and eventually test the manufactured devices.
HardCopy devices use typical ASIC design backend flows to translate a signed-off netlist to layout.
Clock tree synthesis, parasitic extraction, back-annotated static timing analysis (STA) and formal verification are some of the key events in the migration process that Altera performed to ensure the layout maps to the proven design and also mirrors close to the manufactured silicon in functionality and performance.
The IPX-5100 modem needed higher performance from the HardCopy devices compared with the FPGA prototype.
The inherently faster nature of the HardCopy devices over their FPGA counterparts (up to 63% faster) due to the absence of programmability and shorter interconnect lengths stemming from a smaller die size ensured that the HardCopy device met the specifications of IPX-5100 thus satisfying ECC's datarate goals.
Any timing violations discovered during back-annotated STA were fixed with proper buffer insertions and routing constraints.
Once ECC signed-off on the final timing, the database was taped-out for manufacture.
SRAM-based FPGA devices typically require a configuration device that programs the FPGA on power-on and accommodates for rapid design changes.
However, once the design has stabilised, the programmability is unnecessary (and hence the configuration device).
HardCopy devices provide configuration emulation features which not only enabled ECC to retain their existing board and architecture but also voided any necessity to change the software.
The design was checked by ECC and Altera's design engineers to see if it violated industry-standard Design for Testability (DFT) techniques.
The embedded test logic such as scan, memory built-in self test (BIST) and JT structures provided vehicles to test the manufactured device.
Further, ECC did not provide any functional vectors to Altera as the design used structural testing through ATPG vectors resulting in a high quality device.
ECC prototyped their modem and MAC processor design in an FPGA, then migrated their verified design to a HardCopy structured ASIC device to reduce design time, lower manufacturing costs, and increase performance.
HardCopy devices are manufactured as base arrays up to a certain process step ahead of specific designs.
Once the database was ready, design information was routed on the "parked" wafers using the top three metal layers.
Packaged and tested samples were available in less than 7 weeks.
When ECC replaced the FPGA on the board with the HardCopy device, the IPX-5100 worked flawlessly, meeting the system requirements.
The seamless migration of the prototype-proven design delivered fully functional first silicon, enabling the IPX-5100's quick entry in the marketplace with minimum development costs.
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