Structured ASICs take an FPGA design approach

HardCopy II devices are billed as the industry's most compelling structured ASICs, featuring a novel FPGA front-end design methodology and costs as low as $15 for 1 million ASIC gates.

The HardCopy II family is the next-generation structured ASIC solution from Altera Corp.

HardCopy II devices are the industry's most compelling structured ASICs, featuring a unique FPGA front-end design methodology and costs as low as $15 for 1 million ASIC gates.

Built on a new fine-grained architecture designed for low cost, HardCopy II structured ASICs deliver a level of gate densities, performance, and low power consumption that make them the best solution for a broad range of ASIC and ASSP implementations.

HardCopy II devices deliver up to 2.2 million ASIC gates, 8.8Mbit of RAM, and better than 350MHz system performance.

The HardCopy II family's cost, density and performance will extend Altera's reach into the wireline and wireless communication, storage, digital consumer, industrial and military markets, where Altera's structured ASIC solutions are already being successfully adopted.

Huawei's Director of Fixed Network Hardware Jing Yangbao comments: "HardCopy structured ASICs have several advantages compared with standard ASICs".

"The first is lower total cost, the second is shorter development time and faster time to market, and the third is the seamless migration from an FPGA to a HardCopy device".

"With these advantages, we have more options to increase the success of our products".

"Altera's HardCopy structured ASIC gave us the flexibility of an FPGA and the performance of a standard-cell ASIC", said Richard Jaenicke, Director of Product Management at Mercury Computers.

"We compared offerings from other vendors, but they could not meet the cost, performance and time-to-market goals".

"The design and fabrication of the HardCopy devices went very smoothly and the devices were better than advertised - it took us only half a day to verify their functionality and performance".

He continued: "The ability to prototype our designs in the FPGA and quickly get into production with the HardCopy device gave us a time-to-market advantage".

"Based on our experience of using HardCopy devices, we would definitely use them again for a similar project".

Altera offers the only structured ASIC development process with seamless migration from a pin-compatible, functionally equivalent FPGA prototype.

This process minimises development risk and development cost compared with any other ASIC or structured ASIC solution.

Using the Quartus II design software and the Stratix II FPGA family, designers can fully validate their design in system and at speed.

They can also test-market features, and even develop multiple variations of a design, before committing to silicon.

Once engineers finalise their design, the Quartus II design software automatically generates the files to hand off to Altera's HardCopy Design Centre.

The HardCopy Design Centre performs a turnkey migration of the design to a HardCopy II structured ASIC and delivers fully tested prototypes in 8 to 10 weeks.

Collett Research International estimates that more than 60% of ASIC designs need to be re-spun at least once, leading to product delays and cost overruns.

The Altera structured ASIC design methodology helps designers avoid costly respins and lowers the total cost of ownership by dramatically shortening the time it takes to bring a product to market.

With version 4.2 of Altera's Quartus II design software, released in December, designers can prototype their HardCopy II design and lay out their printed circuit board immediately, knowing that Altera's unique seamless migration process will ensure that they will get a true drop-in replacement of their FPGA when they move into production.

"Why choose anything else?", said Jordan Plofsky, Altera's Senior Vice President of Marketing.

"The new price, performance, density, and power features of HardCopy II structured ASICs combined with the FPGA front-end for design verification offers ASIC designers the most efficient methodology for system-level design".

"Additionally, the enormous time-to-market benefit customers derive from Altera's structured ASIC offering is unequaled by any other structured ASIC or standard-cell ASIC solution on the market".

Designers have the option to use their existing synthesis, verification, timing analysis, and logic equivalency checking tools from Cadence, Mentor Graphics, Synopsys and Synplicity.

ASIC and FPGA designers can target HardCopy structured ASICs with their existing design flows, minimising the need for any additional tools training or increased development costs.

HardCopy II devices deliver over 50% core power reduction from the design implemented in the Stratix II FPGA.

Its interface circuitry supports external memory at 233MHz for SDRAM and 250MHz for RLDRAM II.

Additionally, HardCopy II devices also support 1Gbit/s differential I/O and high-speed interfaces, including 10 Gigabit Ethernet (XSBI), SFI-4, SPI 4.2, HyperTransport, RapidIO and Utopia Level 4 interfaces up to 1Gbit/s.

As with the previous HardCopy families, HardCopy II devices are built on the same process as the FPGA used as prototypes, enabling a seamless, risk-free design migration and delivering a drop-in replacement of the FPGA.

HardCopy II devices are manufactured on TSMC's 90nm process with low-k dielectric, the same process as the Stratix II FPGA family.

Designers can immediately begin prototyping their HardCopy II designs on a Stratix II FPGA using Quartus II version 4.2 design software.

Customer prototypes of the first HardCopy II device will be available in the third quarter of 2005.

The HardCopy II family has five members ranging in density between 1 million and 2.2 million ASIC gates.

Volume pricing at 100,000 units starts at $15, with NREs starting at $225,000 for a full turnkey migration, including delivery of fully tested prototypes.

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