Product category:
Programmable Logic Devices
News Release from: Altera Europe | Subject: Stratix II
Edited by the Electronicstalk Editorial
Team on 03 February 2005
FPGAs move to production with upgraded
specs
As its Stratix II FPGA family moves into volume production, Altera has released new specifications reflecting faster performance and lower power.
As its Stratix II FPGA family moves into volume production, Altera Corp has released new specifications reflecting faster performance and lower power With these enhanced specifications, the maximum operating frequencies of the Stratix II family's DSP blocks, internal memories, and high-speed LVDS signalling have increased by up to 20%
This article was originally published on Electronicstalk on 27 May 2008 at 8.00am (UK)
Related stories
Software upgrade provides speed boost
Customers using the 8.0 release to design Altera's 65nm Stratix III FPGAs on Windows platforms will see compile times reduced by up to 50%.
Shrink to 40nm increases FPGA capabilities
The Stratix IV family has up to 680K logic elements, 2x bigger than Altera's Stratix III family, which currently comprise currently the largest FPGAs on the market.
In addition, Stratix II FPGAs consume 45% less static power than previously specified: as low as 0.18W at 25C for the EP2S15 device.
Stratix II devices are the industry's fastest and biggest FPGAs, with 39% better performance on average and 82% more logic elements (LEs) than the closest competing device.
The new specifications give Stratix II FPGAs an additional boost of performance for digital signal processing (DSP), memory, and I/O-intensive applications.
Further reading
FPGAs support serial gigabit interface
Stratix III FPGAs are the industry's first programmable logic devices able to support Gigabit Ethernet SGMII on LVDS pins.
FPGAs support SFI-5 optical comms standard
The SFI-5 specification is a chip-to-chip standard that ensures interoperability between forward-error correction and the framer, as well as from industry-leading optical transponder devices.
Quartus II design software version 4.2 has been updated to enable customers to take advantage of these increases in performance, which include: DSP blocks up from 350 to 420MHz; M-RAM blocks up from 350 to 400MHz; M4K blocks up from 350 to 400MHz; M512 blocks from 370 to 380MHz; LVDS from 800 to 1040Mbit/s; and a demonstrated RLDRAM II clock speed above 440MHz.
"The Stratix II architecture has been designed to maximise performance while virtually eliminating in-rush power and minimising total device power", said David Greenfield, Altera's Senior Director of Product Marketing for High-density FPGAs.
"The stellar performance of Stratix II FPGAs provides a competitive advantage for customers designing high-end systems".
New specifications highlight lower power consumption of the Stratix II family.
For the EP2S60ES device, for example, a surge current of 2A has been eliminated in the production devices, which now exhibit an ideal monotonic rise in power-up current.
This is in addition to the 45% reduction in static power across the Stratix II family.
Furthermore, the Stratix II FPGA total I/O pin capacitance (including silicon, substrate, and package) values range from 3.3 to 6.1pF, which leads to lower total power consumption and is 50% lower than the measured values of the closest competitor's I/O pin capacitance.
Power consumption has two major components, static and dynamic, with dynamic power being the dominant component in total device power.
As dynamic power is design-dependent, accurate power analysis tools are critical to understanding total power consumption.
Altera's PowerPlay power analysis tools found in Quartus II development software are the only tools that accurately estimate total device power for high-density 90nm FPGAs across the full spectrum of operating conditions.
Key capabilities of the power analysis tools include: automatic model generation from Quartus II software; accurate modelling of temperature effects; inclusion of heatsink and airflow settings; use of full logic mapping, placement and routing information; and generation of accurate toggle information from simulation vectors.
• Altera Europe: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
