Software exploits latest FPGA advances

Edited by the Electronicstalk editorial team May 5, 2005

With the release of Quartus II software version 5.0, Altera Corp has announced significant enhancements of Stratix II FPGA specifications that support higher performance and increased flexibility.

With the release of Quartus II software version 5.0, Altera Corp has announced significant enhancements of Stratix II FPGA specifications that support higher performance and increased flexibility.

Quartus II software version 5.0 improves system performance for digital signal processing (DSP), memory, and I/O-intensive design applications incorporating Stratix II FPGAs, which now feature the fastest memory core frequency of any FPGA on the market.

Internal memory block specifications in Stratix II FPGAs have been updated to allow frequencies of up to 550 MHz.

Customers using Quartus II software version 5.0 for designs with Stratix II - the highest-density FPGAs available - can take advantage of these increases in performance: M4K block up from 400 to 550MHz; DSP block from 420 to 450MHz; M512 block from 380 to 500MHz; DDR2 interface (middle speed grade) from 233 to 267MHz; and DDR2 interface (slowest speed grade) up from 200 to 233MHz.

In addition, Quartus II software version 5.0 offers these flexibility enhancements: 1.2V I/O support enabled in Quartus II version 5.0 service pack 1 (SP1); HSTL Class I support on all I/O banks; and DDR2 and RLDRAM II now supported on all I/O banks (including side bank).

"The performance and density of today's high-end FPGAs address a majority of the design starts that historically have used ASICs", said David Greenfield, Altera's Senior Director Of Product Marketing for High-Density FPGAs.

"When coupled with their inherent flexibility, designers increasingly are choosing FPGAs over ASICs for their high-density, high-performance designs".

"This trend is evident with the Stratix II series enjoying significant momentum in the market".