Product category:
Programmable Logic Devices
News Release from: Altera Europe | Subject: Stratix II GX
Edited by the Electronicstalk Editorial
Team on 25 October 2005
FPGAs take serial transceivers onboard
Stratix II GX FPGAs offer a complete programmable solution for the growing number of applications and protocols requiring high-speed serial transceivers.
Altera has launched the Stratix II GX family, its third generation of FPGAs with embedded serial transceivers Designed to deliver superior signal integrity, Stratix II GX FPGAs offer a complete programmable solution for the growing number of applications and protocols requiring high-speed serial transceivers
This article was originally published on Electronicstalk on 24 Jan 2008 at 8.00am (UK)
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Stratix II GX FPGAs combine the industry's fastest and highest-density FPGA fabric with up to 20 low-power transceivers that operate between 622Mbit/s to 6.375Gbit/s to meet the requirements of high-speed designs of today and tomorrow.
Altera carefully selected the data range of the Stratix II GX transceivers based on customer requirements and future protocol roadmaps.
The transceiver blocks provide complete support for a number of widely used protocols, including PCI Express, serial digital interface (SDI), XAUI, Sonet, Gigabit Ethernet, SerialLite II, Serial RapidIO, and Common Electrical Interface 6Gbit/s Long Reach and Short Reach (CEI-6G-LR/SR), saving valuable logic resources and simplifying protocol support.
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Additionally, designers can complete their designs quickly and efficiently by using Altera's comprehensive system solutions that include intellectual property (IP), system models, reference designs, signal integrity tools, and supporting collateral.
Stratix II GX FPGA features help designers simplify the complex task of designing systems that use high-speed protocols.
Stratix II GX FPGAs provide up to 20 full-duplex channels operating between 622Mbit/s and 6.375Gbit/s natively and down to 270Mbit/s using oversampling techniques.
Stratix II GX transceivers optimise the data eye opening using on-chip, dynamically programmable transmit pre-emphasis, receive equalisation and output voltage control.
In addition, through enhanced packaging and chip-design optimisation techniques, standard I/Os are designed to provide best-in-class signal integrity.
Stratix II GX FPGA transceivers consume only 225mW per channel at 6.375Gbit/s - less than half that of the nearest competing FPGA solution.
Stratix II GX FPGAs arrange transceivers in a quad implementation.
Each quad can be driven by two different clock sources, each with access to a high-speed and a low-speed phase-locked loop (PLL).
This combination of clocks and PLLs supports four different datarates and dramatically reduces power dissipation compared with the single PLL implementation found in competing devices.
The Stratix II GX devices' high-density and embedded memory complement the bandwidth and performance of the device transceivers.
Built on TSMC's industry-leading, production-qualified, 90nm process technology, the Stratix II GX family is based on the same FPGA fabric as the Stratix II FPGA family that offers unparalleled, and proven, density, performance, logic efficiency and design security.
"Customers are already leveraging the best-in-class signal integrity of the previous Stratix GX family and the performance and density advantages of the Stratix II family".
"In Stratix II GX FPGAs, we've extended the best features from these device families to meet the needs of the marketplace over the next several years", said Danny Biran, Vice President of Product and Corporate Marketing at Altera.
"System engineers using Stratix II GX FPGAs, along with the complete solutions that we've built around them, have a highly-efficient, low-risk development path for their high-speed designs".
"Our collaboration with Altera in developing and correlating tools that enable modelling, design and manufacturing of robust serial interconnects has yielded excellent results", said John D'Amborsia, Manager, Semiconductor Relations, Tyco Electronics.
"Customers adhering to design methodology recommendations for Stratix II GX FPGAs and Tyco interconnect solutions can expect excellent signal integrity results".
"Our goal is to deliver complete interconnect solutions that are robust and exceed demanding requirements for performance, reliability and value", said Tom Pitten, Vice President of Engineering and Marketing at Teradyne Connection Systems.
"The work we have done with Altera in validating the entire interconnect continues to support this goal and provide system designers with solutions of exceptional signal integrity at leading-edge datarates".
Engineering samples of the first member of the Stratix II GX device family will be available in Q1 2006.
Customers can start their Stratix II GX designs today using HSpice models and Altera's Quartus II design software version 5.1.
Volume prices start at $49 for the EP2SGX30CF780 device.
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