Lightweight serial interconnect runs on FPGAs
New from Altera, SerialLite II is a lightweight serial interconnect protocol for chip-to-chip, board-to-board and backplane applications.
New from Altera, SerialLite II is a lightweight serial interconnect protocol for chip-to-chip, board-to-board and backplane applications.
Optimised for the Stratix II GX device family, the SerialLite II protocol builds on the success of the first-generation SerialLite protocol by supporting a performance range of 622Mbit/s to 6.375Gbit/s while reducing logic requirements by an average of 65%.
SerialLite II delivers a low-cost serial interconnect solution for a wide array of applications, including voice, data and video communication, test and medical, defence, industrial, high-end computing and data storage.
"We worked very closely with our original SerialLite customers to define and develop this second-generation serial protocol", said Justin Cowling, Altera's Director of IP Marketing.
"By understanding the unique requirements of different applications over a widening range of performance points, we were able to define a low-latency, low-overhead protocol with a wider set of configurable features to drive down implementation costs for each customer".
SerialLite II is a point-to-point serial interconnect protocol based on industry-standard 8b/10b encoding, scalable from 1 to 16 lanes at 622Mbit/s to 6.375Gbit/s per lane, for chip-to-chip, board-to-board and backplane applications.
The protocol includes a flexible architecture to support full-duplex (symmetric), simplex, asymmetric and broadcast operation, and support for either streaming or packet data.
The SerialLite II interconnect protocol is available as a MegaCore function which can be downloaded from the Altera website.
A perpetual licence for the MegaCore including one year of upgrades and support is bundled with each subscription of the Quartus II design software.
The annual subscription for the Altera design software is $2000 for a node-locked PC licence.
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