Product category:
Programmable Logic Devices
News Release from: Altera Europe | Subject: Quartus II
Edited by the Electronicstalk Editorial
Team on 09 May 2006
FPGA designers gain ASIC-strength
toolset
Quartus II software is shipping with TimeQuest timing analyser, the first timing analysis tool from an FPGA vendor to provide comprehensive native support for the SDC timing format.
Altera is shipping version 6.0 of its Quartus II software Included in this version is TimeQuest timing analyser, the first timing analysis tool from an FPGA vendor to provide comprehensive native support for the industry-standard Synopsys Design Constraints (SDC) timing format
This article was originally published on Electronicstalk on 27 May 2008 at 8.00am (UK)
Related stories
Software upgrade provides speed boost
Customers using the 8.0 release to design Altera's 65nm Stratix III FPGAs on Windows platforms will see compile times reduced by up to 50%.
Software speeds compiling
A Quartus II software user working with a multiprocessor computer will experience, on average, a 20% reduction in compile times over single-processor computers.
The newest version also includes an expanded team-based design feature that efficiently manages team collaboration of high-density designs.
These advancements address the requirements of today's high-density 90and#8209;nm designs while laying the groundwork for meeting customers' needs for higher FPGA densities and Altera's advance towards its next-generation families at 65nm.
"FPGA designers will be able to achieve timing closure more quickly by directly reading the industry-standard SDC timing constraint format into TimeQuest timing analyser", said Lonn Fiance, director of Strategic Alliances at Synopsys.
Further reading
Low-cost FPGAs released
To immediately start designing with Arria GX devices, customers can use Quartus II design software version 7.1.
FPGA design software doubles productivity
Altera claims its latest software helps designers achieve more than 2x faster compile times and half the memory footprint of the nearest high-end FPGA.
Design and development software for 65nm FPGAs
Quartus II software version 7.0 supports the entire 65nm Cyclone III FPGA family and is available in both subscription and free web editions.
"Adoption of the SDC format will increase productivity among FPGA designers and further advance the deployment of a standard timing verification methodology across the semiconductor industry".
With this latest version of Quartus II software, Altera introduces new technology advancements to meet customer requirements at 90nm and set the stage for the 65nm process node.
The TimeQuest timing analyser is a new, ASIC-strength timing analyser providing comprehensive support for the industry-standard SDC format.
TimeQuest timing analyser enables users to create, manage, and analyse designs with complex timing constraints, such as clock-multiplexed designs and source synchronous interfaces, and to quickly perform advanced timing verification.
TimeQuest timing analyser is available in Quartus II software version 6.0 subscription edition.
Expanded team-based design support includes a project manager interface for managing resource and timing budgets at the top-level design.
Additionally, the project manager interface allows the designer to manage timing constraints between blocks to maximise performance.
This new feature allows teams to collaborate on the design of high-density FPGAs, resulting in improved team productivity and increased performance between design blocks.
This feature builds on the incremental compilation design features first introduced in Quartus II software version 5.0.
SystemVerilog support allows faster register transfer level (RTL) implementation by supporting design constructs of the popular IEEE1800-2005 Standard SystemVerilog syntax hardware description and verification language.
An enhanced I/O pin planner provides easier integration of Altera's intellectual property and simpler pin assignments.
Expanded board-level design support offers HSpice models of Stratix II single-ended outputs for more efficient board modelling.
Quartus II software continues to offer designers a full speed grade advantage for high-density 90nm designs and up to a three speed grade advantage for low-cost 90-nm designs compared with the nearest competitor.
"For designers racing to market with complex, high-density, high-performance FPGA designs, Quartus II software delivers unparalleled advantages".
"It offers the most reliable path to productivity and performance today as the industry designs at 90nm and prepares for 65nm", said Chris Balough, Altera's Director of Software and Nios Marketing.
"Customers continue to rely on Altera to deliver advanced technology in our Quartus II software, such as TimeQuest timing analyser, to help them easily develop powerful designs in the shortest time possible".
Both the subscription edition and the web edition of Quartus II software version 6.0 are now available.
The subscription edition is shipping to all customers with an active software subscription.
The free Quartus II web edition software can be downloaded from the Altera website.
Altera's software subscription programme simplifies the process of obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment.
Subscribers receive the Quartus II software subscription edition, the ModelSim Altera edition and a full licence to the IP Base Suite - nine of Altera's most popular intellectual property cores (DSP, memory and Gigabit Ethernet MAC cores).
The annual software subscription is $2000 for a node-locked PC licence.
Quartus II design software supports major operating systems, including Windows XP Professional x64, Windows XP; Windows 2000; Sun Solaris 8 and 9; and Red Hat Linux Enterprise 3.0 and 4.0.
New or existing customers may obtain a software subscription from Altera distributors worldwide.
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