Product category:
Design and Development Software
News Release from: Altera Europe
Edited by the Electronicstalk Editorial
Team on 24 January 2007
In house estimation tools released to
EDA vendors
Altera Corp is making its PELE pre-emphasis and equalisation link estimator technology available through its EDA partners.
Altera Corp is making its PELE pre-emphasis and equalisation link estimator technology available through its EDA partners to designers who need to estimate the signal integrity settings in its Stratix II GX FPGAs Mentor Graphics Corp is the first EDA partner to integrate PELE into its tool flow
This article was originally published on Electronicstalk on 27 Jun 2008 at 8.00am (UK)
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Originally available only to Altera's internal signal integrity experts, PELE, combined with Mentor Graphics HyperLynx tools, allows high-speed designers to simulate and predict system performance in a matter of hours; otherwise, verifying performance on a laboratory test bench could take months.
"Integrating PELE into our EDA partners' design tools is an essential step for customers to accelerate the design of multi-gigabit transceivers and to get a product to market", said David Greenfield, Senior Director of Product Marketing for High-End FPGAs at Altera.
"Altera is committed to providing the tools to help our customers develop their next-generation systems in the most productive way possible".
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Shrink to 40nm increases FPGA capabilities
The Stratix IV family has up to 680K logic elements, 2x bigger than Altera's Stratix III family, which currently comprise currently the largest FPGAs on the market.
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Stratix III FPGAs are the industry's first programmable logic devices able to support Gigabit Ethernet SGMII on LVDS pins.
Low-cost FPGAs are enhanced for communications
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Using a comprehensive model of the Stratix II GX multigigabit transceiver, PELE technology uses independently extracted or measured frequency-domain characteristics of the customer's serial channels to search for the optimal signal-integrity setting estimate for each of the channel characteristics.
This eliminates guesswork when determining the optimised signal-integrity settings for Stratix II GX FPGAs, which integrate up to 20 low-power transceivers operating between 600Mbit/s and 6.375Gbit/s.
"The combination of HyperLynx and Altera's PELE technology provides our mutual customers with leading-edge tools to design their most advanced systems", stated Dan Boncella, Director of Marketing, Mentor Graphics Corp.
"These capabilities enable users to optimise system performance while reducing their design cycle times".
HyperLynx design tools allow users to extract the frequency-domain S- parameter characteristics of high-speed interconnects from circuit board and backplane layouts, such as the new I-Trac backplane system from Molex.
The way that Altera's PELE technology is embedded into Mentor's design flow ensures file compatibility.
PELE directly imports the frequency- domain S-parameter files from HyperLynx or customer measured data, and configures Mentor's ELDO analogue simulator directly, substantially improving productivity and decreasing design risk.
Users can then take the Stratix II GX ELDO-model outputs and predict the bit error rate (BER) and eye opening over hundreds of billions of bits in a short period of time.
Two papers describing Altera's and Mentor's signal integrity tools will be presented at DesignCon 2007, being held from 29th January to 1st February 2007 in San Jose, California.
The paper titled "Equalisation challenges for 6Gbit/s transceivers addressed by PELE - a software-focused solution" describes PELE and will be presented at 0920 on Tuesday 30th January.
The paper titled "Pre-emphasis and equalisation parameter optimisation with fast, worst-case/multi-billionbit verification", which Altera co-authored with Mentor Graphics Corp and Molex, will discuss a novel, seamless tool flow for signal integrity and will be presented at 0930 on Wednesday 31st January.
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