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News Release from: Altera Europe | Subject: Nios II embedded processor
Edited by the Electronicstalk Editorial
Team on 06 April 2007
Single-chip camera/image processor built
with FPGA
Single-chip camera and image processor is based on an embedded processor integrated with smart image sensors
AnaFocus has chosen Altera's embedded technology to develop Eye-RIS, a single- chip camera and image processor The 0.18um device meets the high-performance control and post-screening video requirements of Eye-RIS's target applications by using Altera's Nios II embedded processor integrated with AnaFocus's smart image sensor (SIS) technology
This article was originally published on Electronicstalk on 15 Nov 2007 at 8.00am (UK)
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By using an Altera FPGA/discrete SIS chip-based development board, AnaFocus was able to quickly create and validate the system architecture for an application with front-end image-processing sensor elements similar to those found in the retina of the human eye.
"We chose Altera's flexible Nios II embedded processor for image post- processing and overall system control of the Eye-RIS system because it enabled us to quickly prototype and validate our system", says Dr Angel Rodriguez- Vazquez, Chief Executive Officer of AnaFocus.
"Adding custom control interfaces and I/O ports to the processor using Altera's SOPC Builder development tool allowed us to develop an optimised architecture for the Eye- RIS vision system while meeting our production schedule and cost targets".
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AnaFocus also enhanced Altera's Eclipse-based Nios II integrated development environment (IDE) by adding custom plug-ins and libraries to create a complete image-processing algorithm design and debug environment for developers of Eye-RIS-based vision systems.
The end result is an integrated, user-friendly IDE that reduces development time for complex vision-processing systems.
By combining SIS technology with the 32bit embedded Nios II processor core, AnaFocus delivers a high-speed, low-power vision system.
SISs differ from CMOS image sensors and CMOS cameras on-chip as image storage and processing circuitry is embedded at the pixel level, intermingled with the sensors where more efficient video processing is carried out.
AnaFocus has developed several generations of SIS architectures but this is the first time a SIS has been used to deliver a single-chip vision system.
The high frame rates, low power consumption and reduced size of this system compared to traditional CCD/CMOS image sensor and digital signal processor solution allows video processing to be applied in many applications where previously the size, cost and power consumption were prohibitive.
Intelligent automotive airbag deployment systems that adapt to the aspect and number of occupants, security surveillance systems with intelligent cameras that can automatically detect, report and track suspicious activity, and vision-based human-computer interfaces for consumer electronic equipment are some of the possible applications.
"Eye-RIS is an excellent example of how the design flexibility and performance of our embedded solutions are enabling new innovations in exciting applications such as vision and imaging", says Chris Balough, Director of Altera's software and embedded marketing.
"It is also evidence of the Nios II processor's ability to easily integrate with other technologies and be efficiently ported to an ASIC implementation".
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