Product category:
Programmable Logic Devices
News Release from: Altera Europe | Subject: Stratix III
Edited by the Electronicstalk Editorial
Team on 13 December 2007
FPGAs race to DDR3 interface speeds
Higher memory bandwidth enables new communications, computing and video processing applications that were either previously impossible or required doubling the number of memory banks.
Altera has achieved DDR3 memory interface speeds in excess of 1067Mbit/s with its Stratix III FPGAs, providing a 33% advantage in memory performance over competing FPGA solutions This higher memory bandwidth enables new communications, computing and video processing applications that were either previously impossible or required doubling the number of memory banks
This article was originally published on Electronicstalk on 10 Nov 2006 at 8.00am (UK)
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FPGAs raise performance but cut power
The Stratix III FPGA family is claimed to deliver the industry's lowest power consumption of any high-density, high-performance programmable logic device.
Coprocessor module built using FPGA
High performance bus to supply additional processing power to Intel Xeon processor-based servers is based on the power of a coprocessor module built using a Stratix III FPGA.
Altera's Stratix III FPGA family is the industry's only FPGA to demonstrate full compliance to the JESD79-3 JEDEC DDR3 SDRAM standard, including the performance-critical read/write-levelling specification for maximum system performance.
"The performance, cost, density, and power benefits that DDR3 memory provides, in conjunction with the highest performance and lowest power of Stratix III FPGAs, is essential to a wide range of communications, signal processing, high-performance computing and image processing applications", says David Greenfield, Senior Director of Product Marketing, High-End Products at Altera.
"Stratix III FPGAs are the only FPGAs designed for fully compliant DDR3 SDRAM DIMM support and the only FPGAs to exceed 533MHz operation".
In addition to higher memory interface speeds, Stratix III FPGAs demonstrate 29% lower power consumption and a 25% performance advantage, as compared with competing solutions, making the device family ideal for high-performance applications that require the lowest possible power.
Designed to address the benefits of DDR3 memory, Altera's Stratix III family is the only FPGA in the industry to include read and write levelling, I/O delay for DQ de-skew, dynamic on-chip termination, and the use of a reconfigurable phase-locked loop (PLL) to compensate for voltage and temperature variations.
In addition, Altera's Quartus II software version 7.2 includes a DDR3 PHY wizard and controller intellectual property (IP), which substantially simplifies high-performance memory interface design by automatically adapting to DIMMs from a variety of memory suppliers.
Altera Stratix III FPGAs featuring DDR3 memory bandwidth capabilities of 533MHz are available now.
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