Altera devices offer XAUI protocol support

Edited by the Electronicstalk editorial team Sep 18, 2008

Altera has announced the availability of a 10Gbit Ethernet (10GbE) reference design that targets designers using the XAUI communications protocol.

Line cards and system controllers used within network routers, enterprise and metro Ethernet switches, and storage switches can use Altera's Arria and Stratix series of FPGAs to connect reliably to 10GbE backplanes or networks.

Altera's 10GbE solution is IEEE 802.3ae standard compliant and has successfully passed the University of New Hampshire Interoperability Lab (UNH-IOL) 10GbE tests.

'Performing testing at the UNH-IOL helps to ensure interoperability with other 10GbE devices and equipment,' said Jeff Lapak, 10Gbit Ethernet consortium manager, UNH-IOL.

Altera said that its 10GbE reference design is a highly reliable and flexible solution, providing all MAC, PCS and PMA functions.

Stratix II GX FPGAs successfully passed all the pertinent UNH 10GbE hardware tests, including Clauses 4 (MAC), 31 (Flow Control), 46 (RS), 47 (XAUI), 48 (10GBASE-X PCS), Clause 54 (CX4), XAUI interoperability tests, and optical module interoperability tests with various optical X2 modules.

The reference design was verified in simulation and hardware tested in Altera's PCI Express Development Kit, Stratix II GX Edition with industry-standard 10GbE test equipment and CX4 and X2 adapters.

Altera's 10GbE reference design consists of an encrypted design library, detailed 10GbE application note, simulation test bench with test cases and user configuration GUI software.

The reference design allows designers to quickly implement Altera's Arria GX, Stratix II GX, Stratix III and Stratix IV GX FPGAs into a multi-10GbE system.

The introduction of Altera's 40nm Stratix IV GX devices enable designers to implement much larger and higher density 10GbE designs with unprecedented FPGA integration levels.

Synthesis options within the reference design include: transmit and receive FIFO of selectable lengths at the MAC-to-system interface for optimising the size of the core and low-latency design; statistics counters supporting RMON (RGC 2819) Ethernet type MIB (RFC 3635) and interface group MIB (RFC 2863); and MDIO management interface for external PHY devices.